476 	unsigned int temp_ctl = 0;  in tsi148_slave_set()  local
538 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
540 	temp_ctl &= ~TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
541 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
559 	temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;  in tsi148_slave_set()
562 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;  in tsi148_slave_set()
565 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;  in tsi148_slave_set()
568 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;  in tsi148_slave_set()
573 	temp_ctl &= ~(0x1F << 7);  in tsi148_slave_set()
575 		temp_ctl |= TSI148_LCSR_ITAT_BLT;  in tsi148_slave_set()
577 		temp_ctl |= TSI148_LCSR_ITAT_MBLT;  in tsi148_slave_set()
579 		temp_ctl |= TSI148_LCSR_ITAT_2eVME;  in tsi148_slave_set()
581 		temp_ctl |= TSI148_LCSR_ITAT_2eSST;  in tsi148_slave_set()
583 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;  in tsi148_slave_set()
586 	temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;  in tsi148_slave_set()
587 	temp_ctl |= addr;  in tsi148_slave_set()
589 	temp_ctl &= ~0xF;  in tsi148_slave_set()
591 		temp_ctl |= TSI148_LCSR_ITAT_SUPR ;  in tsi148_slave_set()
593 		temp_ctl |= TSI148_LCSR_ITAT_NPRIV;  in tsi148_slave_set()
595 		temp_ctl |= TSI148_LCSR_ITAT_PGM;  in tsi148_slave_set()
597 		temp_ctl |= TSI148_LCSR_ITAT_DATA;  in tsi148_slave_set()
600 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
604 		temp_ctl |= TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
606 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
812 	unsigned int temp_ctl = 0;  in tsi148_master_set()  local
902 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
904 	temp_ctl &= ~TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
905 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
909 	temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;  in tsi148_master_set()
912 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;  in tsi148_master_set()
915 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;  in tsi148_master_set()
918 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;  in tsi148_master_set()
924 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
925 		temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;  in tsi148_master_set()
928 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
929 		temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;  in tsi148_master_set()
932 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
933 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;  in tsi148_master_set()
936 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
937 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;  in tsi148_master_set()
942 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
943 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;  in tsi148_master_set()
947 	temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;  in tsi148_master_set()
950 		temp_ctl |= TSI148_LCSR_OTAT_DBW_16;  in tsi148_master_set()
953 		temp_ctl |= TSI148_LCSR_OTAT_DBW_32;  in tsi148_master_set()
963 	temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;  in tsi148_master_set()
966 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;  in tsi148_master_set()
969 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;  in tsi148_master_set()
972 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;  in tsi148_master_set()
975 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;  in tsi148_master_set()
978 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;  in tsi148_master_set()
981 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;  in tsi148_master_set()
984 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;  in tsi148_master_set()
987 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;  in tsi148_master_set()
990 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;  in tsi148_master_set()
999 	temp_ctl &= ~(3<<4);  in tsi148_master_set()
1001 		temp_ctl |= TSI148_LCSR_OTAT_SUP;  in tsi148_master_set()
1003 		temp_ctl |= TSI148_LCSR_OTAT_PGM;  in tsi148_master_set()
1020 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1024 		temp_ctl |= TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
1026 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()