Lines Matching +full:parent +full:- +full:interrupt +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
81 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
85 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
103 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
123 bridge = tsi148_bridge->driver_priv; in tsi148_MB_irqhandler()
127 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
128 dev_err(tsi148_bridge->parent, "VME Mailbox %d received" in tsi148_MB_irqhandler()
138 * Display error & status message when PERR (PCI) exception interrupt occurs.
144 bridge = tsi148_bridge->driver_priv; in tsi148_PERR_irqhandler()
146 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " in tsi148_PERR_irqhandler()
148 ioread32be(bridge->base + TSI148_LCSR_EDPAU), in tsi148_PERR_irqhandler()
149 ioread32be(bridge->base + TSI148_LCSR_EDPAL), in tsi148_PERR_irqhandler()
150 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); in tsi148_PERR_irqhandler()
152 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " in tsi148_PERR_irqhandler()
154 ioread32be(bridge->base + TSI148_LCSR_EDPXA), in tsi148_PERR_irqhandler()
155 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); in tsi148_PERR_irqhandler()
157 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); in tsi148_PERR_irqhandler()
163 * Save address and status when VME error interrupt occurs.
173 bridge = tsi148_bridge->driver_priv; in tsi148_VERR_irqhandler()
175 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); in tsi148_VERR_irqhandler()
176 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); in tsi148_VERR_irqhandler()
177 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); in tsi148_VERR_irqhandler()
184 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " in tsi148_VERR_irqhandler()
191 dev_err(tsi148_bridge->parent, in tsi148_VERR_irqhandler()
196 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); in tsi148_VERR_irqhandler()
206 wake_up(&bridge->iack_queue); in tsi148_IACK_irqhandler()
212 * Calling VME bus interrupt callback if provided.
220 bridge = tsi148_bridge->driver_priv; in tsi148_VIRQ_irqhandler()
222 for (i = 7; i > 0; i--) { in tsi148_VIRQ_irqhandler()
226 * 32-bits in the spec, we only want to issue 8-bit in tsi148_VIRQ_irqhandler()
229 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); in tsi148_VIRQ_irqhandler()
241 * Top level interrupt handler. Clears appropriate interrupt status bits and
252 bridge = tsi148_bridge->driver_priv; in tsi148_irqhandler()
255 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irqhandler()
256 stat = ioread32be(bridge->base + TSI148_LCSR_INTS); in tsi148_irqhandler()
299 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); in tsi148_irqhandler()
311 pdev = to_pci_dev(tsi148_bridge->parent); in tsi148_irq_init()
313 bridge = tsi148_bridge->driver_priv; in tsi148_irq_init()
315 result = request_irq(pdev->irq, in tsi148_irq_init()
320 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " in tsi148_irq_init()
321 "vector %02X\n", pdev->irq); in tsi148_irq_init()
338 /* Don't enable Location Monitor interrupts here - they will be in tsi148_irq_init()
359 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_init()
360 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_init()
368 struct tsi148_driver *bridge = tsi148_bridge->driver_priv; in tsi148_irq_exit()
371 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_exit()
372 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_exit()
375 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); in tsi148_irq_exit()
377 /* Detach interrupt handler */ in tsi148_irq_exit()
378 free_irq(pdev->irq, tsi148_bridge); in tsi148_irq_exit()
388 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_iack_received()
397 * Configure VME interrupt
406 bridge = tsi148_bridge->driver_priv; in tsi148_irq_set()
410 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
411 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; in tsi148_irq_set()
412 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
415 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; in tsi148_irq_set()
416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
419 pdev = to_pci_dev(tsi148_bridge->parent); in tsi148_irq_set()
420 synchronize_irq(pdev->irq); in tsi148_irq_set()
423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
424 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; in tsi148_irq_set()
425 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
428 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; in tsi148_irq_set()
429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
434 * Generate a VME bus interrupt at the requested level & vector. Wait for
435 * interrupt to be acked.
443 bridge = tsi148_bridge->driver_priv; in tsi148_irq_generate()
445 mutex_lock(&bridge->vme_int); in tsi148_irq_generate()
448 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
453 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
457 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
460 wait_event_interruptible(bridge->iack_queue, in tsi148_irq_generate()
463 mutex_unlock(&bridge->vme_int); in tsi148_irq_generate()
484 tsi148_bridge = image->parent; in tsi148_slave_set()
485 bridge = tsi148_bridge->driver_priv; in tsi148_slave_set()
487 i = image->number; in tsi148_slave_set()
507 dev_err(tsi148_bridge->parent, "Invalid address space\n"); in tsi148_slave_set()
508 return -EINVAL; in tsi148_slave_set()
511 /* Convert 64-bit variables to 2x 32-bit variables */ in tsi148_slave_set()
518 vme_bound = vme_base + size - granularity; in tsi148_slave_set()
520 pci_offset = (unsigned long long)pci_base - vme_base; in tsi148_slave_set()
523 if (vme_base_low & (granularity - 1)) { in tsi148_slave_set()
524 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); in tsi148_slave_set()
525 return -EINVAL; in tsi148_slave_set()
527 if (vme_bound_low & (granularity - 1)) { in tsi148_slave_set()
528 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); in tsi148_slave_set()
529 return -EINVAL; in tsi148_slave_set()
531 if (pci_offset_low & (granularity - 1)) { in tsi148_slave_set()
532 dev_err(tsi148_bridge->parent, "Invalid PCI Offset " in tsi148_slave_set()
534 return -EINVAL; in tsi148_slave_set()
538 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
541 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
545 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
547 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
549 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
551 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
553 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
555 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
600 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
606 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
626 bridge = image->parent->driver_priv; in tsi148_slave_get()
628 i = image->number; in tsi148_slave_get()
631 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
634 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
636 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
638 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
640 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
642 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
644 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
647 /* Convert 64-bit variables to 2x 32-bit variables */ in tsi148_slave_get()
679 *size = (unsigned long long)((vme_bound - *vme_base) + granularity); in tsi148_slave_get()
723 tsi148_bridge = image->parent; in tsi148_alloc_resource()
725 pdev = to_pci_dev(tsi148_bridge->parent); in tsi148_alloc_resource()
727 existing_size = (unsigned long long)(image->bus_resource.end - in tsi148_alloc_resource()
728 image->bus_resource.start); in tsi148_alloc_resource()
731 if ((size != 0) && (existing_size == (size - 1))) in tsi148_alloc_resource()
735 iounmap(image->kern_base); in tsi148_alloc_resource()
736 image->kern_base = NULL; in tsi148_alloc_resource()
737 kfree(image->bus_resource.name); in tsi148_alloc_resource()
738 release_resource(&image->bus_resource); in tsi148_alloc_resource()
739 memset(&image->bus_resource, 0, sizeof(image->bus_resource)); in tsi148_alloc_resource()
746 if (!image->bus_resource.name) { in tsi148_alloc_resource()
747 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); in tsi148_alloc_resource()
748 if (!image->bus_resource.name) { in tsi148_alloc_resource()
749 retval = -ENOMEM; in tsi148_alloc_resource()
754 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, in tsi148_alloc_resource()
755 image->number); in tsi148_alloc_resource()
757 image->bus_resource.start = 0; in tsi148_alloc_resource()
758 image->bus_resource.end = (unsigned long)size; in tsi148_alloc_resource()
759 image->bus_resource.flags = IORESOURCE_MEM; in tsi148_alloc_resource()
761 retval = pci_bus_alloc_resource(pdev->bus, in tsi148_alloc_resource()
762 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM, in tsi148_alloc_resource()
765 dev_err(tsi148_bridge->parent, "Failed to allocate mem " in tsi148_alloc_resource()
767 image->number, (unsigned long)size, in tsi148_alloc_resource()
768 (unsigned long)image->bus_resource.start); in tsi148_alloc_resource()
772 image->kern_base = ioremap( in tsi148_alloc_resource()
773 image->bus_resource.start, size); in tsi148_alloc_resource()
774 if (!image->kern_base) { in tsi148_alloc_resource()
775 dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); in tsi148_alloc_resource()
776 retval = -ENOMEM; in tsi148_alloc_resource()
783 release_resource(&image->bus_resource); in tsi148_alloc_resource()
785 kfree(image->bus_resource.name); in tsi148_alloc_resource()
786 memset(&image->bus_resource, 0, sizeof(image->bus_resource)); in tsi148_alloc_resource()
796 iounmap(image->kern_base); in tsi148_free_resource()
797 image->kern_base = NULL; in tsi148_free_resource()
798 release_resource(&image->bus_resource); in tsi148_free_resource()
799 kfree(image->bus_resource.name); in tsi148_free_resource()
800 memset(&image->bus_resource, 0, sizeof(image->bus_resource)); in tsi148_free_resource()
822 tsi148_bridge = image->parent; in tsi148_master_set()
824 bridge = tsi148_bridge->driver_priv; in tsi148_master_set()
826 pdev = to_pci_dev(tsi148_bridge->parent); in tsi148_master_set()
830 dev_err(tsi148_bridge->parent, "Invalid VME Window " in tsi148_master_set()
832 retval = -EINVAL; in tsi148_master_set()
837 dev_err(tsi148_bridge->parent, "Size must be non-zero for " in tsi148_master_set()
839 retval = -EINVAL; in tsi148_master_set()
843 spin_lock(&image->lock); in tsi148_master_set()
851 spin_unlock(&image->lock); in tsi148_master_set()
852 dev_err(tsi148_bridge->parent, "Unable to allocate memory for " in tsi148_master_set()
862 pcibios_resource_to_bus(pdev->bus, ®ion, in tsi148_master_set()
863 &image->bus_resource); in tsi148_master_set()
870 pci_bound = pci_base + (size - 0x10000); in tsi148_master_set()
871 vme_offset = vme_base - pci_base; in tsi148_master_set()
874 /* Convert 64-bit variables to 2x 32-bit variables */ in tsi148_master_set()
880 spin_unlock(&image->lock); in tsi148_master_set()
881 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); in tsi148_master_set()
882 retval = -EINVAL; in tsi148_master_set()
886 spin_unlock(&image->lock); in tsi148_master_set()
887 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); in tsi148_master_set()
888 retval = -EINVAL; in tsi148_master_set()
892 spin_unlock(&image->lock); in tsi148_master_set()
893 dev_err(tsi148_bridge->parent, "Invalid VME Offset " in tsi148_master_set()
895 retval = -EINVAL; in tsi148_master_set()
899 i = image->number; in tsi148_master_set()
902 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
905 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
940 dev_warn(tsi148_bridge->parent, "Currently not setting " in tsi148_master_set()
956 spin_unlock(&image->lock); in tsi148_master_set()
957 dev_err(tsi148_bridge->parent, "Invalid data width\n"); in tsi148_master_set()
958 retval = -EINVAL; in tsi148_master_set()
993 spin_unlock(&image->lock); in tsi148_master_set()
994 dev_err(tsi148_bridge->parent, "Invalid address space\n"); in tsi148_master_set()
995 retval = -EINVAL; in tsi148_master_set()
1006 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1008 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1010 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1012 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1014 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1016 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1020 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1026 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1029 spin_unlock(&image->lock); in tsi148_master_set()
1059 bridge = image->parent->driver_priv; in __tsi148_master_get()
1061 i = image->number; in __tsi148_master_get()
1063 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1066 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1068 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1070 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1072 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1074 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1076 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1079 /* Convert 64-bit variables to 2x 32-bit variables */ in __tsi148_master_get()
1085 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000; in __tsi148_master_get()
1163 spin_lock(&image->lock); in tsi148_master_get()
1168 spin_unlock(&image->lock); in tsi148_master_get()
1181 void __iomem *addr = image->kern_base + offset; in tsi148_master_read()
1185 tsi148_bridge = image->parent; in tsi148_master_read()
1187 spin_lock(&image->lock); in tsi148_master_read()
1195 spin_unlock(&image->lock); in tsi148_master_read()
1196 return -ENOMEM; in tsi148_master_read()
1201 * memcpy_xxx here because it may cut data transfers in to 8-bit in tsi148_master_read()
1205 * automatically for non-aligned addresses, so we don't want the in tsi148_master_read()
1215 if ((count - done) < 2) { in tsi148_master_read()
1225 count32 = (count - done) & ~0x3; in tsi148_master_read()
1231 if ((count - done) & 0x2) { in tsi148_master_read()
1235 if ((count - done) & 0x1) { in tsi148_master_read()
1244 if (handler->num_errors) { in tsi148_master_read()
1245 dev_err(image->parent->parent, in tsi148_master_read()
1247 handler->first_error); in tsi148_master_read()
1248 retval = handler->first_error - (vme_base + offset); in tsi148_master_read()
1253 spin_unlock(&image->lock); in tsi148_master_read()
1265 void __iomem *addr = image->kern_base + offset; in tsi148_master_write()
1273 tsi148_bridge = image->parent; in tsi148_master_write()
1275 bridge = tsi148_bridge->driver_priv; in tsi148_master_write()
1277 spin_lock(&image->lock); in tsi148_master_write()
1285 spin_unlock(&image->lock); in tsi148_master_write()
1286 return -ENOMEM; in tsi148_master_write()
1300 if ((count - done) < 2) { in tsi148_master_write()
1310 count32 = (count - done) & ~0x3; in tsi148_master_write()
1316 if ((count - done) & 0x2) { in tsi148_master_write()
1320 if ((count - done) & 0x1) { in tsi148_master_write()
1332 * that there isn't any read, write re-ordering, so we can read any in tsi148_master_write()
1340 ioread16(bridge->flush_image->kern_base + 0x7F000); in tsi148_master_write()
1342 if (handler->num_errors) { in tsi148_master_write()
1343 dev_warn(tsi148_bridge->parent, in tsi148_master_write()
1345 handler->first_error); in tsi148_master_write()
1346 retval = handler->first_error - (vme_base + offset); in tsi148_master_write()
1351 spin_unlock(&image->lock); in tsi148_master_write()
1371 bridge = image->parent->driver_priv; in tsi148_master_rmw()
1374 i = image->number; in tsi148_master_rmw()
1377 mutex_lock(&bridge->vme_rmw); in tsi148_master_rmw()
1380 spin_lock(&image->lock); in tsi148_master_rmw()
1382 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1384 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1391 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); in tsi148_master_rmw()
1392 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); in tsi148_master_rmw()
1393 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); in tsi148_master_rmw()
1394 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); in tsi148_master_rmw()
1395 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); in tsi148_master_rmw()
1398 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1400 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1403 result = ioread32be(image->kern_base + offset); in tsi148_master_rmw()
1406 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1408 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1410 spin_unlock(&image->lock); in tsi148_master_rmw()
1412 mutex_unlock(&bridge->vme_rmw); in tsi148_master_rmw()
1469 return -EINVAL; in tsi148_dma_set_vme_src_attributes()
1503 return -EINVAL; in tsi148_dma_set_vme_src_attributes()
1568 return -EINVAL; in tsi148_dma_set_vme_dest_attributes()
1602 return -EINVAL; in tsi148_dma_set_vme_dest_attributes()
1631 tsi148_bridge = list->parent->parent; in tsi148_dma_list_add()
1633 /* Descriptor must be aligned on 64-bit boundaries */ in tsi148_dma_list_add()
1636 retval = -ENOMEM; in tsi148_dma_list_add()
1641 if ((unsigned long)&entry->descriptor & 0x7) { in tsi148_dma_list_add()
1642 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " in tsi148_dma_list_add()
1644 &entry->descriptor); in tsi148_dma_list_add()
1645 retval = -EINVAL; in tsi148_dma_list_add()
1652 memset(&entry->descriptor, 0, sizeof(entry->descriptor)); in tsi148_dma_list_add()
1655 switch (src->type) { in tsi148_dma_list_add()
1657 pattern_attr = src->private; in tsi148_dma_list_add()
1659 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern); in tsi148_dma_list_add()
1664 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) in tsi148_dma_list_add()
1668 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) in tsi148_dma_list_add()
1670 entry->descriptor.dsat = cpu_to_be32(val); in tsi148_dma_list_add()
1673 pci_attr = src->private; in tsi148_dma_list_add()
1675 reg_split((unsigned long long)pci_attr->address, &address_high, in tsi148_dma_list_add()
1677 entry->descriptor.dsau = cpu_to_be32(address_high); in tsi148_dma_list_add()
1678 entry->descriptor.dsal = cpu_to_be32(address_low); in tsi148_dma_list_add()
1679 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI); in tsi148_dma_list_add()
1682 vme_attr = src->private; in tsi148_dma_list_add()
1684 reg_split((unsigned long long)vme_attr->address, &address_high, in tsi148_dma_list_add()
1686 entry->descriptor.dsau = cpu_to_be32(address_high); in tsi148_dma_list_add()
1687 entry->descriptor.dsal = cpu_to_be32(address_low); in tsi148_dma_list_add()
1688 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME); in tsi148_dma_list_add()
1691 tsi148_bridge->parent, &entry->descriptor.dsat, in tsi148_dma_list_add()
1692 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1697 dev_err(tsi148_bridge->parent, "Invalid source type\n"); in tsi148_dma_list_add()
1698 retval = -EINVAL; in tsi148_dma_list_add()
1702 /* Assume last link - this will be over-written by adding another */ in tsi148_dma_list_add()
1703 entry->descriptor.dnlau = cpu_to_be32(0); in tsi148_dma_list_add()
1704 entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA); in tsi148_dma_list_add()
1707 switch (dest->type) { in tsi148_dma_list_add()
1709 pci_attr = dest->private; in tsi148_dma_list_add()
1711 reg_split((unsigned long long)pci_attr->address, &address_high, in tsi148_dma_list_add()
1713 entry->descriptor.ddau = cpu_to_be32(address_high); in tsi148_dma_list_add()
1714 entry->descriptor.ddal = cpu_to_be32(address_low); in tsi148_dma_list_add()
1715 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI); in tsi148_dma_list_add()
1718 vme_attr = dest->private; in tsi148_dma_list_add()
1720 reg_split((unsigned long long)vme_attr->address, &address_high, in tsi148_dma_list_add()
1722 entry->descriptor.ddau = cpu_to_be32(address_high); in tsi148_dma_list_add()
1723 entry->descriptor.ddal = cpu_to_be32(address_low); in tsi148_dma_list_add()
1724 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME); in tsi148_dma_list_add()
1727 tsi148_bridge->parent, &entry->descriptor.ddat, in tsi148_dma_list_add()
1728 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1733 dev_err(tsi148_bridge->parent, "Invalid destination type\n"); in tsi148_dma_list_add()
1734 retval = -EINVAL; in tsi148_dma_list_add()
1739 entry->descriptor.dcnt = cpu_to_be32((u32)count); in tsi148_dma_list_add()
1742 list_add_tail(&entry->list, &list->entries); in tsi148_dma_list_add()
1744 entry->dma_handle = dma_map_single(tsi148_bridge->parent, in tsi148_dma_list_add()
1745 &entry->descriptor, in tsi148_dma_list_add()
1746 sizeof(entry->descriptor), in tsi148_dma_list_add()
1748 if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) { in tsi148_dma_list_add()
1749 dev_err(tsi148_bridge->parent, "DMA mapping error\n"); in tsi148_dma_list_add()
1750 retval = -EINVAL; in tsi148_dma_list_add()
1755 if (entry->list.prev != &list->entries) { in tsi148_dma_list_add()
1756 reg_split((unsigned long long)entry->dma_handle, &address_high, in tsi148_dma_list_add()
1758 prev = list_entry(entry->list.prev, struct tsi148_dma_entry, in tsi148_dma_list_add()
1760 prev->descriptor.dnlau = cpu_to_be32(address_high); in tsi148_dma_list_add()
1761 prev->descriptor.dnlal = cpu_to_be32(address_low); in tsi148_dma_list_add()
1784 bridge = tsi148_bridge->driver_priv; in tsi148_dma_busy()
1786 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_busy()
1811 ctrlr = list->parent; in tsi148_dma_list_exec()
1813 tsi148_bridge = ctrlr->parent; in tsi148_dma_list_exec()
1815 bridge = tsi148_bridge->driver_priv; in tsi148_dma_list_exec()
1817 mutex_lock(&ctrlr->mtx); in tsi148_dma_list_exec()
1819 channel = ctrlr->number; in tsi148_dma_list_exec()
1821 if (!list_empty(&ctrlr->running)) { in tsi148_dma_list_exec()
1828 mutex_unlock(&ctrlr->mtx); in tsi148_dma_list_exec()
1829 return -EBUSY; in tsi148_dma_list_exec()
1831 list_add(&list->list, &ctrlr->running); in tsi148_dma_list_exec()
1835 entry = list_first_entry(&list->entries, struct tsi148_dma_entry, in tsi148_dma_list_exec()
1838 mutex_unlock(&ctrlr->mtx); in tsi148_dma_list_exec()
1840 reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low); in tsi148_dma_list_exec()
1842 iowrite32be(bus_addr_high, bridge->base + in tsi148_dma_list_exec()
1844 iowrite32be(bus_addr_low, bridge->base + in tsi148_dma_list_exec()
1847 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1851 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + in tsi148_dma_list_exec()
1854 retval = wait_event_interruptible(bridge->dma_queue[channel], in tsi148_dma_list_exec()
1855 tsi148_dma_busy(ctrlr->parent, channel)); in tsi148_dma_list_exec()
1858 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base + in tsi148_dma_list_exec()
1861 wait_event(bridge->dma_queue[channel], in tsi148_dma_list_exec()
1862 tsi148_dma_busy(ctrlr->parent, channel)); in tsi148_dma_list_exec()
1863 retval = -EINTR; in tsi148_dma_list_exec()
1871 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1875 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); in tsi148_dma_list_exec()
1876 retval = -EIO; in tsi148_dma_list_exec()
1881 mutex_lock(&ctrlr->mtx); in tsi148_dma_list_exec()
1882 list_del(&list->list); in tsi148_dma_list_exec()
1883 mutex_unlock(&ctrlr->mtx); in tsi148_dma_list_exec()
1898 struct vme_bridge *tsi148_bridge = list->parent->parent; in tsi148_dma_list_empty()
1901 list_for_each_safe(pos, temp, &list->entries) { in tsi148_dma_list_empty()
1905 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle, in tsi148_dma_list_empty()
1914 * All 4 location monitors reside at the same base - this is therefore a
1917 * This does not enable the LM monitor - that should be done when the first
1928 tsi148_bridge = lm->parent; in tsi148_lm_set()
1930 bridge = tsi148_bridge->driver_priv; in tsi148_lm_set()
1932 mutex_lock(&lm->mtx); in tsi148_lm_set()
1935 for (i = 0; i < lm->monitors; i++) { in tsi148_lm_set()
1936 if (bridge->lm_callback[i]) { in tsi148_lm_set()
1937 mutex_unlock(&lm->mtx); in tsi148_lm_set()
1938 dev_err(tsi148_bridge->parent, "Location monitor " in tsi148_lm_set()
1940 return -EBUSY; in tsi148_lm_set()
1958 mutex_unlock(&lm->mtx); in tsi148_lm_set()
1959 dev_err(tsi148_bridge->parent, "Invalid address space\n"); in tsi148_lm_set()
1960 return -EINVAL; in tsi148_lm_set()
1974 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); in tsi148_lm_set()
1975 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); in tsi148_lm_set()
1976 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_set()
1978 mutex_unlock(&lm->mtx); in tsi148_lm_set()
1992 bridge = lm->parent->driver_priv; in tsi148_lm_get()
1994 mutex_lock(&lm->mtx); in tsi148_lm_get()
1996 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); in tsi148_lm_get()
1997 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); in tsi148_lm_get()
1998 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_get()
2027 mutex_unlock(&lm->mtx); in tsi148_lm_get()
2044 tsi148_bridge = lm->parent; in tsi148_lm_attach()
2046 bridge = tsi148_bridge->driver_priv; in tsi148_lm_attach()
2048 mutex_lock(&lm->mtx); in tsi148_lm_attach()
2050 /* Ensure that the location monitor is configured - need PGM or DATA */ in tsi148_lm_attach()
2051 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_attach()
2053 mutex_unlock(&lm->mtx); in tsi148_lm_attach()
2054 dev_err(tsi148_bridge->parent, "Location monitor not properly " in tsi148_lm_attach()
2056 return -EINVAL; in tsi148_lm_attach()
2060 if (bridge->lm_callback[monitor]) { in tsi148_lm_attach()
2061 mutex_unlock(&lm->mtx); in tsi148_lm_attach()
2062 dev_err(tsi148_bridge->parent, "Existing callback attached\n"); in tsi148_lm_attach()
2063 return -EBUSY; in tsi148_lm_attach()
2067 bridge->lm_callback[monitor] = callback; in tsi148_lm_attach()
2068 bridge->lm_data[monitor] = data; in tsi148_lm_attach()
2070 /* Enable Location Monitor interrupt */ in tsi148_lm_attach()
2071 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_attach()
2073 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_attach()
2075 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_attach()
2077 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_attach()
2082 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_attach()
2085 mutex_unlock(&lm->mtx); in tsi148_lm_attach()
2098 bridge = lm->parent->driver_priv; in tsi148_lm_detach()
2100 mutex_lock(&lm->mtx); in tsi148_lm_detach()
2103 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_detach()
2105 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_detach()
2107 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_detach()
2109 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_detach()
2112 bridge->base + TSI148_LCSR_INTC); in tsi148_lm_detach()
2115 bridge->lm_callback[monitor] = NULL; in tsi148_lm_detach()
2116 bridge->lm_data[monitor] = NULL; in tsi148_lm_detach()
2121 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_detach()
2123 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_detach()
2126 mutex_unlock(&lm->mtx); in tsi148_lm_detach()
2139 bridge = tsi148_bridge->driver_priv; in tsi148_slot_get()
2142 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); in tsi148_slot_get()
2150 static void *tsi148_alloc_consistent(struct device *parent, size_t size, in tsi148_alloc_consistent() argument
2156 pdev = to_pci_dev(parent); in tsi148_alloc_consistent()
2158 return dma_alloc_coherent(&pdev->dev, size, dma, GFP_KERNEL); in tsi148_alloc_consistent()
2161 static void tsi148_free_consistent(struct device *parent, size_t size, in tsi148_free_consistent() argument
2167 pdev = to_pci_dev(parent); in tsi148_free_consistent()
2169 dma_free_coherent(&pdev->dev, size, vaddr, dma); in tsi148_free_consistent()
2175 * Access to the CR/CSR can be configured at power-up. The location of the
2177 * Auto-ID or Geographic address. This function ensures that the window is
2192 bridge = tsi148_bridge->driver_priv; in tsi148_crcsr_init()
2195 bridge->crcsr_kernel = dma_alloc_coherent(&pdev->dev, in tsi148_crcsr_init()
2197 &bridge->crcsr_bus, GFP_KERNEL); in tsi148_crcsr_init()
2198 if (!bridge->crcsr_kernel) { in tsi148_crcsr_init()
2199 dev_err(tsi148_bridge->parent, "Failed to allocate memory for " in tsi148_crcsr_init()
2201 return -ENOMEM; in tsi148_crcsr_init()
2204 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); in tsi148_crcsr_init()
2206 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); in tsi148_crcsr_init()
2207 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); in tsi148_crcsr_init()
2210 cbar = ioread32be(bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2217 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); in tsi148_crcsr_init()
2218 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2220 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); in tsi148_crcsr_init()
2222 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_init()
2224 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); in tsi148_crcsr_init()
2226 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); in tsi148_crcsr_init()
2228 bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_init()
2231 /* If we want flushed, error-checked writes, set up a window in tsi148_crcsr_init()
2236 retval = tsi148_master_set(bridge->flush_image, 1, in tsi148_crcsr_init()
2240 dev_err(tsi148_bridge->parent, "Configuring flush image" in tsi148_crcsr_init()
2254 bridge = tsi148_bridge->driver_priv; in tsi148_crcsr_exit()
2257 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_exit()
2259 bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_exit()
2262 iowrite32be(0, bridge->base + TSI148_LCSR_CROU); in tsi148_crcsr_exit()
2263 iowrite32be(0, bridge->base + TSI148_LCSR_CROL); in tsi148_crcsr_exit()
2265 dma_free_coherent(&pdev->dev, VME_CRCSR_BUF_SIZE, in tsi148_crcsr_exit()
2266 bridge->crcsr_kernel, bridge->crcsr_bus); in tsi148_crcsr_exit()
2286 retval = -ENOMEM; in tsi148_probe()
2293 retval = -ENOMEM; in tsi148_probe()
2297 tsi148_bridge->driver_priv = tsi148_device; in tsi148_probe()
2302 dev_err(&pdev->dev, "Unable to enable device\n"); in tsi148_probe()
2309 dev_err(&pdev->dev, "Unable to reserve resources\n"); in tsi148_probe()
2314 tsi148_device->base = ioremap(pci_resource_start(pdev, 0), in tsi148_probe()
2316 if (!tsi148_device->base) { in tsi148_probe()
2317 dev_err(&pdev->dev, "Unable to remap CRG region\n"); in tsi148_probe()
2318 retval = -EIO; in tsi148_probe()
2323 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; in tsi148_probe()
2325 dev_err(&pdev->dev, "CRG region check failed\n"); in tsi148_probe()
2326 retval = -EIO; in tsi148_probe()
2331 init_waitqueue_head(&tsi148_device->dma_queue[0]); in tsi148_probe()
2332 init_waitqueue_head(&tsi148_device->dma_queue[1]); in tsi148_probe()
2333 init_waitqueue_head(&tsi148_device->iack_queue); in tsi148_probe()
2334 mutex_init(&tsi148_device->vme_int); in tsi148_probe()
2335 mutex_init(&tsi148_device->vme_rmw); in tsi148_probe()
2337 tsi148_bridge->parent = &pdev->dev; in tsi148_probe()
2338 strcpy(tsi148_bridge->name, driver_name); in tsi148_probe()
2343 dev_err(&pdev->dev, "Chip Initialization failed.\n"); in tsi148_probe()
2354 master_num--; in tsi148_probe()
2356 tsi148_device->flush_image = in tsi148_probe()
2357 kmalloc(sizeof(*tsi148_device->flush_image), in tsi148_probe()
2359 if (!tsi148_device->flush_image) { in tsi148_probe()
2360 retval = -ENOMEM; in tsi148_probe()
2363 tsi148_device->flush_image->parent = tsi148_bridge; in tsi148_probe()
2364 spin_lock_init(&tsi148_device->flush_image->lock); in tsi148_probe()
2365 tsi148_device->flush_image->locked = 1; in tsi148_probe()
2366 tsi148_device->flush_image->number = master_num; in tsi148_probe()
2367 memset(&tsi148_device->flush_image->bus_resource, 0, in tsi148_probe()
2368 sizeof(tsi148_device->flush_image->bus_resource)); in tsi148_probe()
2369 tsi148_device->flush_image->kern_base = NULL; in tsi148_probe()
2376 retval = -ENOMEM; in tsi148_probe()
2379 master_image->parent = tsi148_bridge; in tsi148_probe()
2380 spin_lock_init(&master_image->lock); in tsi148_probe()
2381 master_image->locked = 0; in tsi148_probe()
2382 master_image->number = i; in tsi148_probe()
2383 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | in tsi148_probe()
2386 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | in tsi148_probe()
2390 master_image->width_attr = VME_D16 | VME_D32; in tsi148_probe()
2391 memset(&master_image->bus_resource, 0, in tsi148_probe()
2392 sizeof(master_image->bus_resource)); in tsi148_probe()
2393 master_image->kern_base = NULL; in tsi148_probe()
2394 list_add_tail(&master_image->list, in tsi148_probe()
2395 &tsi148_bridge->master_resources); in tsi148_probe()
2402 retval = -ENOMEM; in tsi148_probe()
2405 slave_image->parent = tsi148_bridge; in tsi148_probe()
2406 mutex_init(&slave_image->mtx); in tsi148_probe()
2407 slave_image->locked = 0; in tsi148_probe()
2408 slave_image->number = i; in tsi148_probe()
2409 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 | in tsi148_probe()
2411 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | in tsi148_probe()
2415 list_add_tail(&slave_image->list, in tsi148_probe()
2416 &tsi148_bridge->slave_resources); in tsi148_probe()
2423 retval = -ENOMEM; in tsi148_probe()
2426 dma_ctrlr->parent = tsi148_bridge; in tsi148_probe()
2427 mutex_init(&dma_ctrlr->mtx); in tsi148_probe()
2428 dma_ctrlr->locked = 0; in tsi148_probe()
2429 dma_ctrlr->number = i; in tsi148_probe()
2430 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | in tsi148_probe()
2434 INIT_LIST_HEAD(&dma_ctrlr->pending); in tsi148_probe()
2435 INIT_LIST_HEAD(&dma_ctrlr->running); in tsi148_probe()
2436 list_add_tail(&dma_ctrlr->list, in tsi148_probe()
2437 &tsi148_bridge->dma_resources); in tsi148_probe()
2443 retval = -ENOMEM; in tsi148_probe()
2446 lm->parent = tsi148_bridge; in tsi148_probe()
2447 mutex_init(&lm->mtx); in tsi148_probe()
2448 lm->locked = 0; in tsi148_probe()
2449 lm->number = 1; in tsi148_probe()
2450 lm->monitors = 4; in tsi148_probe()
2451 list_add_tail(&lm->list, &tsi148_bridge->lm_resources); in tsi148_probe()
2453 tsi148_bridge->slave_get = tsi148_slave_get; in tsi148_probe()
2454 tsi148_bridge->slave_set = tsi148_slave_set; in tsi148_probe()
2455 tsi148_bridge->master_get = tsi148_master_get; in tsi148_probe()
2456 tsi148_bridge->master_set = tsi148_master_set; in tsi148_probe()
2457 tsi148_bridge->master_read = tsi148_master_read; in tsi148_probe()
2458 tsi148_bridge->master_write = tsi148_master_write; in tsi148_probe()
2459 tsi148_bridge->master_rmw = tsi148_master_rmw; in tsi148_probe()
2460 tsi148_bridge->dma_list_add = tsi148_dma_list_add; in tsi148_probe()
2461 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec; in tsi148_probe()
2462 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty; in tsi148_probe()
2463 tsi148_bridge->irq_set = tsi148_irq_set; in tsi148_probe()
2464 tsi148_bridge->irq_generate = tsi148_irq_generate; in tsi148_probe()
2465 tsi148_bridge->lm_set = tsi148_lm_set; in tsi148_probe()
2466 tsi148_bridge->lm_get = tsi148_lm_get; in tsi148_probe()
2467 tsi148_bridge->lm_attach = tsi148_lm_attach; in tsi148_probe()
2468 tsi148_bridge->lm_detach = tsi148_lm_detach; in tsi148_probe()
2469 tsi148_bridge->slot_get = tsi148_slot_get; in tsi148_probe()
2470 tsi148_bridge->alloc_consistent = tsi148_alloc_consistent; in tsi148_probe()
2471 tsi148_bridge->free_consistent = tsi148_free_consistent; in tsi148_probe()
2473 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); in tsi148_probe()
2474 dev_info(&pdev->dev, "Board is%s the VME system controller\n", in tsi148_probe()
2477 dev_info(&pdev->dev, "VME geographical address is %d\n", in tsi148_probe()
2480 dev_info(&pdev->dev, "VME geographical address is set to %d\n", in tsi148_probe()
2483 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", in tsi148_probe()
2488 dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); in tsi148_probe()
2494 dev_err(&pdev->dev, "Chip Registration failed.\n"); in tsi148_probe()
2500 /* Clear VME bus "board fail", and "power-up reset" lines */ in tsi148_probe()
2501 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); in tsi148_probe()
2504 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); in tsi148_probe()
2513 list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) { in tsi148_probe()
2520 list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) { in tsi148_probe()
2527 list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) { in tsi148_probe()
2534 list_for_each_safe(pos, n, &tsi148_bridge->master_resources) { in tsi148_probe()
2544 iounmap(tsi148_device->base); in tsi148_probe()
2569 bridge = tsi148_bridge->driver_priv; in tsi148_remove()
2572 dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); in tsi148_remove()
2578 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + in tsi148_remove()
2580 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + in tsi148_remove()
2587 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); in tsi148_remove()
2592 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); in tsi148_remove()
2597 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); in tsi148_remove()
2598 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); in tsi148_remove()
2599 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); in tsi148_remove()
2602 * Remove VIRQ interrupt (if any) in tsi148_remove()
2604 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) in tsi148_remove()
2605 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); in tsi148_remove()
2610 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); in tsi148_remove()
2611 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); in tsi148_remove()
2620 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) { in tsi148_remove()
2627 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) { in tsi148_remove()
2634 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) { in tsi148_remove()
2641 iounmap(bridge->base); in tsi148_remove()
2647 kfree(tsi148_bridge->driver_priv); in tsi148_remove()