473 	dma_addr_t pci_base, u32 aspace, u32 cycle)  in tsi148_slave_set()  argument
560 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_slave_set()
572 	/* Setup cycle types */  in tsi148_slave_set()
574 	if (cycle & VME_BLT)  in tsi148_slave_set()
576 	if (cycle & VME_MBLT)  in tsi148_slave_set()
578 	if (cycle & VME_2eVME)  in tsi148_slave_set()
580 	if (cycle & VME_2eSST)  in tsi148_slave_set()
582 	if (cycle & VME_2eSSTB)  in tsi148_slave_set()
590 	if (cycle & VME_SUPER)  in tsi148_slave_set()
592 	if (cycle & VME_USER)  in tsi148_slave_set()
594 	if (cycle & VME_PROG)  in tsi148_slave_set()
596 	if (cycle & VME_DATA)  in tsi148_slave_set()
617 	dma_addr_t *pci_base, u32 *aspace, u32 *cycle)  in tsi148_slave_get()  argument
656 	*cycle = 0;  in tsi148_slave_get()
683 		*cycle |= VME_2eSST160;  in tsi148_slave_get()
685 		*cycle |= VME_2eSST267;  in tsi148_slave_get()
687 		*cycle |= VME_2eSST320;  in tsi148_slave_get()
690 		*cycle |= VME_BLT;  in tsi148_slave_get()
692 		*cycle |= VME_MBLT;  in tsi148_slave_get()
694 		*cycle |= VME_2eVME;  in tsi148_slave_get()
696 		*cycle |= VME_2eSST;  in tsi148_slave_get()
698 		*cycle |= VME_2eSSTB;  in tsi148_slave_get()
701 		*cycle |= VME_SUPER;  in tsi148_slave_get()
703 		*cycle |= VME_USER;  in tsi148_slave_get()
705 		*cycle |= VME_PROG;  in tsi148_slave_get()
707 		*cycle |= VME_DATA;  in tsi148_slave_get()
808 	u32 cycle, u32 dwidth)  in tsi148_master_set()  argument
910 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_master_set()
922 	/* Setup cycle types */  in tsi148_master_set()
923 	if (cycle & VME_BLT) {  in tsi148_master_set()
927 	if (cycle & VME_MBLT) {  in tsi148_master_set()
931 	if (cycle & VME_2eVME) {  in tsi148_master_set()
935 	if (cycle & VME_2eSST) {  in tsi148_master_set()
939 	if (cycle & VME_2eSSTB) {  in tsi148_master_set()
1000 	if (cycle & VME_SUPER)  in tsi148_master_set()
1002 	if (cycle & VME_PROG)  in tsi148_master_set()
1049 	u32 *cycle, u32 *dwidth)  in __tsi148_master_get()  argument
1089 	*cycle = 0;  in __tsi148_master_get()
1117 		*cycle |= VME_2eSST160;  in __tsi148_master_get()
1119 		*cycle |= VME_2eSST267;  in __tsi148_master_get()
1121 		*cycle |= VME_2eSST320;  in __tsi148_master_get()
1123 	/* Setup cycle types */  in __tsi148_master_get()
1125 		*cycle |= VME_SCT;  in __tsi148_master_get()
1127 		*cycle |= VME_BLT;  in __tsi148_master_get()
1129 		*cycle |= VME_MBLT;  in __tsi148_master_get()
1131 		*cycle |= VME_2eVME;  in __tsi148_master_get()
1133 		*cycle |= VME_2eSST;  in __tsi148_master_get()
1135 		*cycle |= VME_2eSSTB;  in __tsi148_master_get()
1138 		*cycle |= VME_SUPER;  in __tsi148_master_get()
1140 		*cycle |= VME_USER;  in __tsi148_master_get()
1143 		*cycle |= VME_PROG;  in __tsi148_master_get()
1145 		*cycle |= VME_DATA;  in __tsi148_master_get()
1159 	u32 *cycle, u32 *dwidth)  in tsi148_master_get()  argument
1166 		cycle, dwidth);  in tsi148_master_get()
1178 	u32 aspace, cycle, dwidth;  in tsi148_master_read()  local
1191 				    &cycle, &dwidth);  in tsi148_master_read()
1204 	 * cycle configured for the transfer is used and splits it  in tsi148_master_read()
1206 	 * overhead of needlessly forcing small transfers for the entire cycle.  in tsi148_master_read()
1264 	u32 aspace, cycle, dwidth;  in tsi148_master_write()  local
1281 				    &cycle, &dwidth);  in tsi148_master_write()
1357  * Perform an RMW cycle on the VME bus.
1418 	u32 aspace, u32 cycle, u32 dwidth)  in tsi148_dma_set_vme_src_attributes()  argument
1425 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_dma_set_vme_src_attributes()
1437 	/* Setup cycle types */  in tsi148_dma_set_vme_src_attributes()
1438 	if (cycle & VME_SCT)  in tsi148_dma_set_vme_src_attributes()
1441 	if (cycle & VME_BLT)  in tsi148_dma_set_vme_src_attributes()
1444 	if (cycle & VME_MBLT)  in tsi148_dma_set_vme_src_attributes()
1447 	if (cycle & VME_2eVME)  in tsi148_dma_set_vme_src_attributes()
1450 	if (cycle & VME_2eSST)  in tsi148_dma_set_vme_src_attributes()
1453 	if (cycle & VME_2eSSTB) {  in tsi148_dma_set_vme_src_attributes()
1506 	if (cycle & VME_SUPER)  in tsi148_dma_set_vme_src_attributes()
1508 	if (cycle & VME_PROG)  in tsi148_dma_set_vme_src_attributes()
1517 	u32 aspace, u32 cycle, u32 dwidth)  in tsi148_dma_set_vme_dest_attributes()  argument
1524 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_dma_set_vme_dest_attributes()
1536 	/* Setup cycle types */  in tsi148_dma_set_vme_dest_attributes()
1537 	if (cycle & VME_SCT)  in tsi148_dma_set_vme_dest_attributes()
1540 	if (cycle & VME_BLT)  in tsi148_dma_set_vme_dest_attributes()
1543 	if (cycle & VME_MBLT)  in tsi148_dma_set_vme_dest_attributes()
1546 	if (cycle & VME_2eVME)  in tsi148_dma_set_vme_dest_attributes()
1549 	if (cycle & VME_2eSST)  in tsi148_dma_set_vme_dest_attributes()
1552 	if (cycle & VME_2eSSTB) {  in tsi148_dma_set_vme_dest_attributes()
1605 	if (cycle & VME_SUPER)  in tsi148_dma_set_vme_dest_attributes()
1607 	if (cycle & VME_PROG)  in tsi148_dma_set_vme_dest_attributes()
1692 			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);  in tsi148_dma_list_add()
1728 			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);  in tsi148_dma_list_add()
1921 	u32 aspace, u32 cycle)  in tsi148_lm_set()  argument
1963 	if (cycle & VME_SUPER)  in tsi148_lm_set()
1965 	if (cycle & VME_USER)  in tsi148_lm_set()
1967 	if (cycle & VME_PROG)  in tsi148_lm_set()
1969 	if (cycle & VME_DATA)  in tsi148_lm_set()
1987 	unsigned long long *lm_base, u32 *aspace, u32 *cycle)  in tsi148_lm_get()  argument
2019 		*cycle |= VME_SUPER;  in tsi148_lm_get()
2021 		*cycle |= VME_USER;  in tsi148_lm_get()
2023 		*cycle |= VME_PROG;  in tsi148_lm_get()
2025 		*cycle |= VME_DATA;  in tsi148_lm_get()