666 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,  in calc_vclock()  argument
672 	m = (5 * (m1 + 2)) + (m2 + 2);  in calc_vclock()
716 	int i, m1, m2, n, p1, p2;  in intelfbhw_print_hw_state()  local
728 	m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;  in intelfbhw_print_hw_state()
733 	printk("	VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",  in intelfbhw_print_hw_state()
734 	       m1, m2, n, p1, p2);  in intelfbhw_print_hw_state()
736 	       calc_vclock(index, m1, m2, n, p1, p2, 0));  in intelfbhw_print_hw_state()
739 	m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;  in intelfbhw_print_hw_state()
743 	printk("	VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",  in intelfbhw_print_hw_state()
744 	       m1, m2, n, p1, p2);  in intelfbhw_print_hw_state()
746 	       calc_vclock(index, m1, m2, n, p1, p2, 0));  in intelfbhw_print_hw_state()
756 	m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;  in intelfbhw_print_hw_state()
761 	printk("	PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",  in intelfbhw_print_hw_state()
762 	       m1, m2, n, p1, p2);  in intelfbhw_print_hw_state()
764 	       calc_vclock(index, m1, m2, n, p1, p2, 0));  in intelfbhw_print_hw_state()
767 	m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;  in intelfbhw_print_hw_state()
772 	printk("	PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",  in intelfbhw_print_hw_state()
773 	       m1, m2, n, p1, p2);  in intelfbhw_print_hw_state()
775 	       calc_vclock(index, m1, m2, n, p1, p2, 0));  in intelfbhw_print_hw_state()
879 /* Split the M parameter into M1 and M2. */
883 	int m1, m2;  in splitm()  local
888 	for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {  in splitm()
890 			testm = (5 * (m1 + 2)) + (m2 + 2);  in splitm()
892 				*retm1 = (unsigned int)m1;  in splitm()
940 	u32 m1, m2, n, p1, p2, n1, testm;  in calc_pll_params()  local
979 				if (splitm(index, testm, &m1, &m2)) {  in calc_pll_params()
1008 	splitm(index, m, &m1, &m2);  in calc_pll_params()
1014 		m, m1, m2, n, n1, p, p1, p2,  in calc_pll_params()
1016 		calc_vclock(index, m1, m2, n1, p1, p2, 0),  in calc_pll_params()
1018 	*retm1 = m1;  in calc_pll_params()
1023 	*retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);  in calc_pll_params()
1046 	u32 m1, m2, n, p1, p2, clock_target, clock;  in intelfbhw_mode_to_hw()  local
1115 	if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,  in intelfbhw_mode_to_hw()
1126 	if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))  in intelfbhw_mode_to_hw()
1144 	       (m1 << FP_M1_DIVISOR_SHIFT) |  in intelfbhw_mode_to_hw()