18 #define PCI_DEVICE_ID_IBM_GXT4500P	0x21c
19 #define PCI_DEVICE_ID_IBM_GXT6500P	0x21b
20 #define PCI_DEVICE_ID_IBM_GXT4000P	0x16e
21 #define PCI_DEVICE_ID_IBM_GXT6000P	0x170
26 #define CFG_ENDIAN0		0x40
29 #define STATUS			0x1000
30 #define CTRL_REG0		0x1004
31 #define   CR0_HALT_DMA			0x4
32 #define   CR0_RASTER_RESET		0x8
33 #define   CR0_GEOM_RESET		0x10
34 #define   CR0_MEM_CTRLER_RESET		0x20
37 #define FB_AB_CTRL		0x1100
38 #define FB_CD_CTRL		0x1104
39 #define FB_WID_CTRL		0x1108
40 #define FB_Z_CTRL		0x110c
41 #define FB_VGA_CTRL		0x1110
42 #define REFRESH_AB_CTRL		0x1114
43 #define REFRESH_CD_CTRL		0x1118
44 #define FB_OVL_CTRL		0x111c
45 #define   FB_CTRL_TYPE			0x80000000
46 #define   FB_CTRL_WIDTH_MASK		0x007f0000
48 #define   FB_CTRL_START_SEG_MASK	0x00003fff
50 #define REFRESH_START		0x1098
51 #define REFRESH_SIZE		0x109c
54 #define DFA_FB_A		0x11e0
55 #define DFA_FB_B		0x11e4
56 #define DFA_FB_C		0x11e8
57 #define DFA_FB_D		0x11ec
58 #define   DFA_FB_ENABLE			0x80000000
59 #define   DFA_FB_BASE_MASK		0x03f00000
60 #define   DFA_FB_STRIDE_1k		0x00000000
61 #define   DFA_FB_STRIDE_2k		0x00000010
62 #define   DFA_FB_STRIDE_4k		0x00000020
63 #define   DFA_PIX_8BIT			0x00000000
64 #define   DFA_PIX_16BIT_565		0x00000001
65 #define   DFA_PIX_16BIT_1555		0x00000002
66 #define   DFA_PIX_24BIT			0x00000004
67 #define   DFA_PIX_32BIT			0x00000005
75 #define DTG_CONTROL		0x1900
78 #define DTG_HORIZ_EXTENT	0x1904
79 #define DTG_HORIZ_DISPLAY	0x1908
80 #define DTG_HSYNC_START		0x190c
81 #define DTG_HSYNC_END		0x1910
82 #define DTG_HSYNC_END_COMP	0x1914
83 #define DTG_VERT_EXTENT		0x1918
84 #define DTG_VERT_DISPLAY	0x191c
85 #define DTG_VSYNC_START		0x1920
86 #define DTG_VSYNC_END		0x1924
87 #define DTG_VERT_SHORT		0x1928
90 #define DISP_CTL		0x402c
92 #define SYNC_CTL		0x4034
96 #define   SYNC_CTL_VSYNC_INV		0x10
97 #define   SYNC_CTL_HSYNC_OFF		0x20
98 #define   SYNC_CTL_VSYNC_OFF		0x40
100 #define PLL_M			0x4040
101 #define PLL_N			0x4044
102 #define PLL_POSTDIV		0x4048
103 #define PLL_C			0x404c
106 #define CURSOR_X		0x4078
107 #define CURSOR_Y		0x407c
108 #define CURSOR_HOTSPOT		0x4080
109 #define CURSOR_MODE		0x4084
110 #define   CURSOR_MODE_OFF		0
112 #define CURSOR_PIXMAP		0x5000
113 #define CURSOR_CMAP		0x7400
116 #define WAT_FMT			0x4100
117 #define   WAT_FMT_24BIT			0
120 #define   WAT_FMT_32BIT			3	/* 0 vs. 3 is a guess */
122 #define   WAT_FMT_8BIT			0xa
124 #define WAT_CMAP_OFFSET		0x4104		/* 4-bit value gets << 6 */
125 #define WAT_CTRL		0x4108
128 #define WAT_GAMMA_CTRL		0x410c
130 #define WAT_OVL_CTRL		0x430c		/* controls overlay */
134 	WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
139 #define CMAP			0x6000
207 /* 1 */		      0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
208 /* 10 */	0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
209 /* 20 */	0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
210 /* 30 */	0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
211 /* 40 */	0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
212 /* 50 */	0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
213 /* 60 */	0x1f, 0x0f, 0x07, 0x03, 0x01,
217 /* 2 */		            0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
218 /* 10 */	0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
219 /* 20 */	0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
220 /* 30 */	0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
221 /* 40 */	0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
222 /* 50 */	0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
223 /* 60 */	0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
224 /* 70 */	0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
225 /* 80 */	0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
226 /* 90 */	0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
227 /* 100 */	0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
228 /* 110 */	0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
229 /* 120 */	0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
230 /* 130 */	0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
231 /* 140 */	0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
232 /* 150 */	0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
233 /* 160 */	0x69,
262 				if (t >= 0 && t < best_error) {  in calc_pll()
274 	return 0;  in calc_pll()
293 	if (calc_pll(var->pixclock, par) < 0)  in gxt4500_var_to_par()
319 	return 0;  in gxt4500_var_to_par()
322 static const struct fb_bitfield eightbits = {0, 8};
323 static const struct fb_bitfield nobits = {0, 0};
351 		var->blue.offset = 0;  in gxt4500_unpack_pixfmt()
399 	tmp = readreg(par, PLL_C) & ~0x7f;  in gxt4500_set_par()
401 		tmp |= 0x29;  in gxt4500_set_par()
403 		tmp |= 0x35;  in gxt4500_set_par()
405 		tmp |= 0x76;  in gxt4500_set_par()
407 		tmp |= 0x7e;  in gxt4500_set_par()
414 		writereg(par, PLL_POSTDIV, tmp | 0x9);  in gxt4500_set_par()
468 	writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);  in gxt4500_set_par()
469 	writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);  in gxt4500_set_par()
470 	writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);  in gxt4500_set_par()
471 	writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);  in gxt4500_set_par()
486 	for (i = 0; i < 32; ++i) {  in gxt4500_set_par()
488 		writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);  in gxt4500_set_par()
489 		writereg(par, WAT_CTRL + (i << 4), 0);  in gxt4500_set_par()
509 	return 0;  in gxt4500_set_par()
521 	cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |  in gxt4500_setcolreg()
522 		(green & 0xff00) | (blue >> 8);  in gxt4500_setcolreg()
545 	return 0;  in gxt4500_setcolreg()
560 	return 0;  in gxt4500_pan_display()
590 	return 0;  in gxt4500_blank()
599 	.mmio_len = 0x20000,
631 	reg_phys = pci_resource_start(pdev, 0);  in gxt4500_probe()
632 	if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),  in gxt4500_probe()
658 	par->regs = pci_ioremap_bar(pdev, 0);  in gxt4500_probe()
679 	pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);  in gxt4500_probe()
682 	pci_write_config_dword(pdev, CFG_ENDIAN0, 0x2300);  in gxt4500_probe()
683 /*	pci_write_config_dword(pdev, CFG_ENDIAN0 + 4, 0x400000);*/  in gxt4500_probe()
684 	pci_write_config_dword(pdev, CFG_ENDIAN0 + 8, 0x98530000);  in gxt4500_probe()
691 	err = fb_alloc_cmap(&info->cmap, 256, 0);  in gxt4500_probe()
699 	if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {  in gxt4500_probe()
709 	if (register_framebuffer(info) < 0) {  in gxt4500_probe()
715 	return 0;  in gxt4500_probe()
728 	release_mem_region(reg_phys, pci_resource_len(pdev, 0));  in gxt4500_probe()
746 	release_mem_region(pci_resource_start(pdev, 0),  in gxt4500_remove()
747 			   pci_resource_len(pdev, 0));  in gxt4500_remove()
763 	{ 0 }
795 module_param(mode_option, charp, 0);