Lines Matching defs:cg14_regs
101 struct cg14_regs{ struct
102 u8 mcr; /* Master Control Reg */
103 u8 ppr; /* Packed Pixel Reg */
104 u8 tms[2]; /* Test Mode Status Regs */
105 u8 msr; /* Master Status Reg */
106 u8 fsr; /* Fault Status Reg */
107 u8 rev; /* Revision & Impl */
108 u8 ccr; /* Clock Control Reg */
109 u32 tmr; /* Test Mode Read Back */
110 u8 mod; /* Monitor Operation Data Reg */
111 u8 acr; /* Aux Control */
112 u8 xxx0[6];
113 u16 hct; /* Hor Counter */
114 u16 vct; /* Vert Counter */
115 u16 hbs; /* Hor Blank Start */
116 u16 hbc; /* Hor Blank Clear */
117 u16 hss; /* Hor Sync Start */
118 u16 hsc; /* Hor Sync Clear */
119 u16 csc; /* Composite Sync Clear */
120 u16 vbs; /* Vert Blank Start */
121 u16 vbc; /* Vert Blank Clear */
122 u16 vss; /* Vert Sync Start */
123 u16 vsc; /* Vert Sync Clear */
124 u16 xcs;
125 u16 xcc;
126 u16 fsa; /* Fault Status Address */
127 u16 adr; /* Address Registers */
128 u8 xxx1[0xce];
129 u8 pcg[0x100]; /* Pixel Clock Generator */
130 u32 vbr; /* Frame Base Row */
131 u32 vmcr; /* VBC Master Control */
132 u32 vcr; /* VBC refresh */
133 u32 vca; /* VBC Config */