154 #define CH341_CLK_DIV(ps, fact)	(1 << (12 - 3 * (ps) - (fact)))  argument
171  *	baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
174  *		0 <= fact <= 1,
175  *		2 <= div <= 256 if fact = 0, or
176  *		9 <= div <= 256 if fact = 1
180 	unsigned int fact, div, clk_div;  in ch341_get_divisor()  local
191 	 * Start with highest possible base clock (fact = 1) that will give a  in ch341_get_divisor()
194 	fact = 1;  in ch341_get_divisor()
204 	clk_div = CH341_CLK_DIV(ps, fact);  in ch341_get_divisor()
211 	/* Halve base clock (fact = 0) if required. */  in ch341_get_divisor()
215 		fact = 0;  in ch341_get_divisor()
230 	 * Prefer lower base clock (fact = 0) if even divisor.  in ch341_get_divisor()
234 	if (fact == 1 && div % 2 == 0) {  in ch341_get_divisor()
236 		fact = 0;  in ch341_get_divisor()
239 	return (0x100 - div) << 8 | fact << 2 | ps;  in ch341_get_divisor()