Lines Matching refs:val
216 u32 val; in set_pts() local
219 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
220 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
221 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
222 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
224 val = readl_relaxed(base + TEGRA_USB_PORTSC1); in set_pts()
225 val &= ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
226 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
227 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
228 writel_relaxed(val, base + TEGRA_USB_PORTSC1); in set_pts()
235 u32 val; in set_phcd() local
238 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
240 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; in set_phcd()
242 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; in set_phcd()
243 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
245 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; in set_phcd()
247 val |= TEGRA_USB_PORTSC1_PHCD; in set_phcd()
249 val &= ~TEGRA_USB_PORTSC1_PHCD; in set_phcd()
250 writel_relaxed(val, base + TEGRA_USB_PORTSC1); in set_phcd()
322 u32 val; in utmip_pad_power_on() local
332 val = readl_relaxed(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
333 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); in utmip_pad_power_on()
336 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | in utmip_pad_power_on()
340 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); in utmip_pad_power_on()
341 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); in utmip_pad_power_on()
342 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); in utmip_pad_power_on()
344 writel_relaxed(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
362 u32 val; in utmip_pad_power_off() local
389 val = readl_relaxed(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
390 val |= UTMIP_OTGPD | UTMIP_BIASPD; in utmip_pad_power_off()
391 writel_relaxed(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
412 u32 val; in utmi_phy_clk_disable() local
423 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
424 val |= USB_SUSP_SET; in utmi_phy_clk_disable()
425 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
429 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
430 val &= ~USB_SUSP_SET; in utmi_phy_clk_disable()
431 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
444 u32 val; in utmi_phy_clk_enable() local
456 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
457 val |= USB_SUSP_CLR; in utmi_phy_clk_enable()
458 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
462 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
463 val &= ~USB_SUSP_CLR; in utmi_phy_clk_enable()
464 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
479 u32 val; in utmi_phy_power_on() local
482 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
483 val |= UTMIP_RESET; in utmi_phy_power_on()
484 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
487 val = readl_relaxed(base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
488 val |= USB1_NO_LEGACY_MODE; in utmi_phy_power_on()
489 writel_relaxed(val, base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
492 val = readl_relaxed(base + UTMIP_TX_CFG0); in utmi_phy_power_on()
493 val |= UTMIP_FS_PREABMLE_J; in utmi_phy_power_on()
494 writel_relaxed(val, base + UTMIP_TX_CFG0); in utmi_phy_power_on()
496 val = readl_relaxed(base + UTMIP_HSRX_CFG0); in utmi_phy_power_on()
497 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); in utmi_phy_power_on()
498 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); in utmi_phy_power_on()
499 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); in utmi_phy_power_on()
500 writel_relaxed(val, base + UTMIP_HSRX_CFG0); in utmi_phy_power_on()
502 val = readl_relaxed(base + UTMIP_HSRX_CFG1); in utmi_phy_power_on()
503 val &= ~UTMIP_HS_SYNC_START_DLY(~0); in utmi_phy_power_on()
504 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); in utmi_phy_power_on()
505 writel_relaxed(val, base + UTMIP_HSRX_CFG1); in utmi_phy_power_on()
507 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0); in utmi_phy_power_on()
508 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); in utmi_phy_power_on()
509 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); in utmi_phy_power_on()
510 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0); in utmi_phy_power_on()
512 val = readl_relaxed(base + UTMIP_MISC_CFG0); in utmi_phy_power_on()
513 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; in utmi_phy_power_on()
514 writel_relaxed(val, base + UTMIP_MISC_CFG0); in utmi_phy_power_on()
517 val = readl_relaxed(base + UTMIP_MISC_CFG1); in utmi_phy_power_on()
518 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | in utmi_phy_power_on()
520 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | in utmi_phy_power_on()
522 writel_relaxed(val, base + UTMIP_MISC_CFG1); in utmi_phy_power_on()
524 val = readl_relaxed(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()
525 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | in utmi_phy_power_on()
527 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | in utmi_phy_power_on()
529 writel_relaxed(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()
532 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
533 val &= ~USB_WAKE_ON_RESUME_EN; in utmi_phy_power_on()
534 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
537 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
538 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); in utmi_phy_power_on()
539 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
541 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); in utmi_phy_power_on()
542 val &= ~VBUS_WAKEUP_WAKEUP_EN; in utmi_phy_power_on()
543 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); in utmi_phy_power_on()
545 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); in utmi_phy_power_on()
546 val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN); in utmi_phy_power_on()
547 val &= ~(B_SESS_VLD_WAKEUP_EN); in utmi_phy_power_on()
548 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); in utmi_phy_power_on()
550 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
551 val &= ~UTMIP_PD_CHRG; in utmi_phy_power_on()
552 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
554 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
555 val |= UTMIP_PD_CHRG; in utmi_phy_power_on()
556 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
563 val = readl_relaxed(base + UTMIP_XCVR_CFG0); in utmi_phy_power_on()
564 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | in utmi_phy_power_on()
570 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); in utmi_phy_power_on()
571 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); in utmi_phy_power_on()
573 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); in utmi_phy_power_on()
574 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); in utmi_phy_power_on()
577 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); in utmi_phy_power_on()
578 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); in utmi_phy_power_on()
579 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); in utmi_phy_power_on()
581 writel_relaxed(val, base + UTMIP_XCVR_CFG0); in utmi_phy_power_on()
583 val = readl_relaxed(base + UTMIP_XCVR_CFG1); in utmi_phy_power_on()
584 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | in utmi_phy_power_on()
586 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); in utmi_phy_power_on()
587 writel_relaxed(val, base + UTMIP_XCVR_CFG1); in utmi_phy_power_on()
589 val = readl_relaxed(base + UTMIP_BIAS_CFG1); in utmi_phy_power_on()
590 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); in utmi_phy_power_on()
591 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); in utmi_phy_power_on()
592 writel_relaxed(val, base + UTMIP_BIAS_CFG1); in utmi_phy_power_on()
594 val = readl_relaxed(base + UTMIP_SPARE_CFG0); in utmi_phy_power_on()
596 val |= FUSE_SETUP_SEL; in utmi_phy_power_on()
598 val &= ~FUSE_SETUP_SEL; in utmi_phy_power_on()
599 writel_relaxed(val, base + UTMIP_SPARE_CFG0); in utmi_phy_power_on()
602 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
603 val |= UTMIP_PHY_ENABLE; in utmi_phy_power_on()
604 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
607 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
608 val &= ~UTMIP_RESET; in utmi_phy_power_on()
609 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
612 val = readl_relaxed(base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
613 val &= ~USB1_VBUS_SENSE_CTL_MASK; in utmi_phy_power_on()
614 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; in utmi_phy_power_on()
615 writel_relaxed(val, base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
617 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_on()
618 val &= ~USB_SUSP_SET; in utmi_phy_power_on()
619 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
625 val = readl_relaxed(base + USB_USBMODE); in utmi_phy_power_on()
626 val &= ~USB_USBMODE_MASK; in utmi_phy_power_on()
628 val |= USB_USBMODE_HOST; in utmi_phy_power_on()
630 val |= USB_USBMODE_DEVICE; in utmi_phy_power_on()
631 writel_relaxed(val, base + USB_USBMODE); in utmi_phy_power_on()
643 u32 val; in utmi_phy_power_off() local
651 val, !(val & VBUS_WAKEUP_STS), in utmi_phy_power_off()
658 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_off()
659 val |= UTMIP_RESET; in utmi_phy_power_off()
660 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_off()
663 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_off()
664 val |= UTMIP_PD_CHRG; in utmi_phy_power_off()
665 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_off()
668 val = readl_relaxed(base + UTMIP_XCVR_CFG0); in utmi_phy_power_off()
669 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | in utmi_phy_power_off()
671 writel_relaxed(val, base + UTMIP_XCVR_CFG0); in utmi_phy_power_off()
674 val = readl_relaxed(base + UTMIP_XCVR_CFG1); in utmi_phy_power_off()
675 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | in utmi_phy_power_off()
677 writel_relaxed(val, base + UTMIP_XCVR_CFG1); in utmi_phy_power_off()
680 val = readl_relaxed(base + USB_SUSP_CTRL); in utmi_phy_power_off()
681 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); in utmi_phy_power_off()
682 val |= USB_WAKEUP_DEBOUNCE_COUNT(5); in utmi_phy_power_off()
683 val |= USB_WAKE_ON_RESUME_EN; in utmi_phy_power_off()
684 writel_relaxed(val, base + USB_SUSP_CTRL); in utmi_phy_power_off()
691 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); in utmi_phy_power_off()
692 val |= VBUS_WAKEUP_WAKEUP_EN; in utmi_phy_power_off()
693 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); in utmi_phy_power_off()
695 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); in utmi_phy_power_off()
696 val |= A_VBUS_VLD_WAKEUP_EN; in utmi_phy_power_off()
697 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); in utmi_phy_power_off()
707 u32 val; in utmi_phy_preresume() local
709 val = readl_relaxed(base + UTMIP_TX_CFG0); in utmi_phy_preresume()
710 val |= UTMIP_HS_DISCON_DISABLE; in utmi_phy_preresume()
711 writel_relaxed(val, base + UTMIP_TX_CFG0); in utmi_phy_preresume()
717 u32 val; in utmi_phy_postresume() local
719 val = readl_relaxed(base + UTMIP_TX_CFG0); in utmi_phy_postresume()
720 val &= ~UTMIP_HS_DISCON_DISABLE; in utmi_phy_postresume()
721 writel_relaxed(val, base + UTMIP_TX_CFG0); in utmi_phy_postresume()
728 u32 val; in utmi_phy_restore_start() local
730 val = readl_relaxed(base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
731 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); in utmi_phy_restore_start()
733 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; in utmi_phy_restore_start()
735 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; in utmi_phy_restore_start()
736 writel_relaxed(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
739 val = readl_relaxed(base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
740 val |= UTMIP_DPDM_OBSERVE; in utmi_phy_restore_start()
741 writel_relaxed(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
748 u32 val; in utmi_phy_restore_end() local
750 val = readl_relaxed(base + UTMIP_MISC_CFG0); in utmi_phy_restore_end()
751 val &= ~UTMIP_DPDM_OBSERVE; in utmi_phy_restore_end()
752 writel_relaxed(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_end()
759 u32 val; in ulpi_phy_power_on() local
774 val = readl_relaxed(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
775 val |= UHSIC_RESET; in ulpi_phy_power_on()
776 writel_relaxed(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
778 val = readl_relaxed(base + ULPI_TIMING_CTRL_0); in ulpi_phy_power_on()
779 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; in ulpi_phy_power_on()
780 writel_relaxed(val, base + ULPI_TIMING_CTRL_0); in ulpi_phy_power_on()
782 val = readl_relaxed(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
783 val |= ULPI_PHY_ENABLE; in ulpi_phy_power_on()
784 writel_relaxed(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
786 val = 0; in ulpi_phy_power_on()
787 writel_relaxed(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
789 val |= ULPI_DATA_TRIMMER_SEL(4); in ulpi_phy_power_on()
790 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); in ulpi_phy_power_on()
791 val |= ULPI_DIR_TRIMMER_SEL(4); in ulpi_phy_power_on()
792 writel_relaxed(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
795 val |= ULPI_DATA_TRIMMER_LOAD; in ulpi_phy_power_on()
796 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; in ulpi_phy_power_on()
797 val |= ULPI_DIR_TRIMMER_LOAD; in ulpi_phy_power_on()
798 writel_relaxed(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
813 val = readl_relaxed(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
814 val |= USB_SUSP_CLR; in ulpi_phy_power_on()
815 writel_relaxed(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
818 val = readl_relaxed(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
819 val &= ~USB_SUSP_CLR; in ulpi_phy_power_on()
820 writel_relaxed(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()