Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
13 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
74 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
76 /* Allocation size (8, 16, 32, ... 4096) */
121 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
122 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
125 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
202 #define MUSB_FADDR 0x00 /* 8-bit */
203 #define MUSB_POWER 0x01 /* 8-bit */
205 #define MUSB_INTRTX 0x02 /* 16-bit */
209 #define MUSB_INTRUSB 0x0A /* 8 bit */
210 #define MUSB_INTRUSBE 0x0B /* 8 bit */
212 #define MUSB_INDEX 0x0E /* 8 bit */
213 #define MUSB_TESTMODE 0x0F /* 8 bit */
219 #define MUSB_DEVCTL 0x60 /* 8 bit */
220 #define MUSB_BABBLE_CTL 0x61 /* 8 bit */
223 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
224 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
225 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
226 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
229 #define MUSB_HWVERS 0x6C /* 8 bit */
230 #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
231 #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
232 #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
233 #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
234 #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
235 #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
236 #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
238 #define MUSB_EPINFO 0x78 /* 8 bit */
239 #define MUSB_RAMINFO 0x79 /* 8 bit */
240 #define MUSB_LINKINFO 0x7a /* 8 bit */
241 #define MUSB_VPLEN 0x7b /* 8 bit */
242 #define MUSB_HS_EOF1 0x7c /* 8 bit */
243 #define MUSB_FS_EOF1 0x7d /* 8 bit */
244 #define MUSB_LS_EOF1 0x7e /* 8 bit */
249 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
253 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
255 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
257 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
261 #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
285 musb_writeb(musb->mregs, in musb_write_rxfunaddr()
286 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR), in musb_write_rxfunaddr()
293 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR), in musb_write_rxhubaddr()
300 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT), in musb_write_rxhubport()
307 musb_writeb(musb->mregs, in musb_write_txfunaddr()
308 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR), in musb_write_txfunaddr()
315 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR), in musb_write_txhubaddr()
322 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT), in musb_write_txhubport()
328 return musb_readb(musb->mregs, in musb_read_rxfunaddr()
329 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR)); in musb_read_rxfunaddr()
334 return musb_readb(musb->mregs, in musb_read_rxhubaddr()
335 musb->io.busctl_offset(epnum, MUSB_RXHUBADDR)); in musb_read_rxhubaddr()
340 return musb_readb(musb->mregs, in musb_read_rxhubport()
341 musb->io.busctl_offset(epnum, MUSB_RXHUBPORT)); in musb_read_rxhubport()
346 return musb_readb(musb->mregs, in musb_read_txfunaddr()
347 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR)); in musb_read_txfunaddr()
352 return musb_readb(musb->mregs, in musb_read_txhubaddr()
353 musb->io.busctl_offset(epnum, MUSB_TXHUBADDR)); in musb_read_txhubaddr()
358 return musb_readb(musb->mregs, in musb_read_txhubport()
359 musb->io.busctl_offset(epnum, MUSB_TXHUBPORT)); in musb_read_txhubport()