229 	u16			fifo_count = 0, csr;  in txstate()  local
248 	csr = musb_readw(epio, MUSB_TXCSR);  in txstate()
254 	if (csr & MUSB_TXCSR_TXPKTRDY) {  in txstate()
256 				musb_ep->end_point.name, csr);  in txstate()
260 	if (csr & MUSB_TXCSR_P_SENDSTALL) {  in txstate()
262 				musb_ep->end_point.name, csr);  in txstate()
268 			csr);  in txstate()
275 		/* setup DMA, then program endpoint CSR */  in txstate()
301 					csr &= ~(MUSB_TXCSR_AUTOSET  in txstate()
303 					musb_writew(epio, MUSB_TXCSR, csr  in txstate()
305 					csr &= ~MUSB_TXCSR_DMAMODE;  in txstate()
306 					csr |= (MUSB_TXCSR_DMAENAB |  in txstate()
310 					csr |= (MUSB_TXCSR_DMAENAB  in txstate()
325 						csr |= MUSB_TXCSR_AUTOSET;  in txstate()
327 				csr &= ~MUSB_TXCSR_P_UNDERRUN;  in txstate()
329 				musb_writew(epio, MUSB_TXCSR, csr);  in txstate()
334 			/* program endpoint CSR first, then setup DMA */  in txstate()
335 			csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);  in txstate()
336 			csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |  in txstate()
339 						~MUSB_TXCSR_P_UNDERRUN) | csr);  in txstate()
342 			csr = musb_readw(epio, MUSB_TXCSR);  in txstate()
365 				csr &= ~MUSB_TXCSR_DMAENAB;  in txstate()
366 				musb_writew(epio, MUSB_TXCSR, csr);  in txstate()
388 		csr |= MUSB_TXCSR_TXPKTRDY;  in txstate()
389 		csr &= ~MUSB_TXCSR_P_UNDERRUN;  in txstate()
390 		musb_writew(epio, MUSB_TXCSR, csr);  in txstate()
408 	u16			csr;  in musb_g_tx()  local
420 	csr = musb_readw(epio, MUSB_TXCSR);  in musb_g_tx()
421 	musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);  in musb_g_tx()
429 	if (csr & MUSB_TXCSR_P_SENTSTALL) {  in musb_g_tx()
430 		csr |=	MUSB_TXCSR_P_WZC_BITS;  in musb_g_tx()
431 		csr &= ~MUSB_TXCSR_P_SENTSTALL;  in musb_g_tx()
432 		musb_writew(epio, MUSB_TXCSR, csr);  in musb_g_tx()
436 	if (csr & MUSB_TXCSR_P_UNDERRUN) {  in musb_g_tx()
438 		csr |=	 MUSB_TXCSR_P_WZC_BITS;  in musb_g_tx()
439 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);  in musb_g_tx()
440 		musb_writew(epio, MUSB_TXCSR, csr);  in musb_g_tx()
458 		if (dma && (csr & MUSB_TXCSR_DMAENAB)) {  in musb_g_tx()
459 			csr |= MUSB_TXCSR_P_WZC_BITS;  in musb_g_tx()
460 			csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |  in musb_g_tx()
462 			musb_writew(epio, MUSB_TXCSR, csr);  in musb_g_tx()
464 			csr = musb_readw(epio, MUSB_TXCSR);  in musb_g_tx()
467 				epnum, csr, musb_ep->dma->actual_len, request);  in musb_g_tx()
482 			if (csr & MUSB_TXCSR_TXPKTRDY)  in musb_g_tx()
526 	u16			csr = musb_readw(epio, MUSB_RXCSR);  in rxstate()  local
550 	if (csr & MUSB_RXCSR_P_SENDSTALL) {  in rxstate()
552 		    musb_ep->end_point.name, csr);  in rxstate()
575 			csr &= ~(MUSB_RXCSR_AUTOCLEAR  in rxstate()
577 			csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;  in rxstate()
578 			musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
583 	if (csr & MUSB_RXCSR_RXPKTRDY) {  in rxstate()
633 					csr |= MUSB_RXCSR_AUTOCLEAR;  in rxstate()
634 					musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
635 					csr |= MUSB_RXCSR_DMAENAB;  in rxstate()
636 					musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
644 						csr | MUSB_RXCSR_DMAMODE);  in rxstate()
645 					musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
655 						csr |= MUSB_RXCSR_AUTOCLEAR;  in rxstate()
656 					csr |= MUSB_RXCSR_DMAENAB;  in rxstate()
657 					musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
700 				csr &= ~MUSB_RXCSR_DMAMODE;  in rxstate()
701 				csr |= (MUSB_RXCSR_DMAENAB |  in rxstate()
704 				musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
711 					csr |= MUSB_RXCSR_DMAMODE;  in rxstate()
712 					musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
759 			csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);  in rxstate()
760 			musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
772 			csr |= MUSB_RXCSR_P_WZC_BITS;  in rxstate()
773 			csr &= ~MUSB_RXCSR_RXPKTRDY;  in rxstate()
774 			musb_writew(epio, MUSB_RXCSR, csr);  in rxstate()
789 	u16			csr;  in musb_g_rx()  local
812 	csr = musb_readw(epio, MUSB_RXCSR);  in musb_g_rx()
816 			csr, dma ? " (dma)" : "", request);  in musb_g_rx()
818 	if (csr & MUSB_RXCSR_P_SENTSTALL) {  in musb_g_rx()
819 		csr |= MUSB_RXCSR_P_WZC_BITS;  in musb_g_rx()
820 		csr &= ~MUSB_RXCSR_P_SENTSTALL;  in musb_g_rx()
821 		musb_writew(epio, MUSB_RXCSR, csr);  in musb_g_rx()
825 	if (csr & MUSB_RXCSR_P_OVERRUN) {  in musb_g_rx()
826 		/* csr |= MUSB_RXCSR_P_WZC_BITS; */  in musb_g_rx()
827 		csr &= ~MUSB_RXCSR_P_OVERRUN;  in musb_g_rx()
828 		musb_writew(epio, MUSB_RXCSR, csr);  in musb_g_rx()
834 	if (csr & MUSB_RXCSR_INCOMPRX) {  in musb_g_rx()
841 		musb_dbg(musb, "%s busy, csr %04x",  in musb_g_rx()
842 			musb_ep->end_point.name, csr);  in musb_g_rx()
846 	if (dma && (csr & MUSB_RXCSR_DMAENAB)) {  in musb_g_rx()
847 		csr &= ~(MUSB_RXCSR_AUTOCLEAR  in musb_g_rx()
851 			MUSB_RXCSR_P_WZC_BITS | csr);  in musb_g_rx()
862 			csr &= ~MUSB_RXCSR_RXPKTRDY;  in musb_g_rx()
863 			musb_writew(epio, MUSB_RXCSR, csr);  in musb_g_rx()
873 			csr = musb_readw(epio, MUSB_RXCSR);  in musb_g_rx()
874 			if ((csr & MUSB_RXCSR_RXPKTRDY) &&  in musb_g_rx()
915 	u16		csr;  in musb_gadget_enable()  local
994 		csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;  in musb_gadget_enable()
997 			csr |= MUSB_TXCSR_FLUSHFIFO;  in musb_gadget_enable()
999 			csr |= MUSB_TXCSR_P_ISO;  in musb_gadget_enable()
1002 		musb_writew(regs, MUSB_TXCSR, csr);  in musb_gadget_enable()
1004 		musb_writew(regs, MUSB_TXCSR, csr);  in musb_gadget_enable()
1032 			csr = musb_readw(regs, MUSB_TXCSR);  in musb_gadget_enable()
1033 			csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);  in musb_gadget_enable()
1034 			musb_writew(regs, MUSB_TXCSR, csr);  in musb_gadget_enable()
1037 		csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;  in musb_gadget_enable()
1039 			csr |= MUSB_RXCSR_P_ISO;  in musb_gadget_enable()
1041 			csr |= MUSB_RXCSR_DISNYET;  in musb_gadget_enable()
1044 		musb_writew(regs, MUSB_RXCSR, csr);  in musb_gadget_enable()
1045 		musb_writew(regs, MUSB_RXCSR, csr);  in musb_gadget_enable()
1331 	u16			csr;  in musb_gadget_set_halt()  local
1358 			csr = musb_readw(epio, MUSB_TXCSR);  in musb_gadget_set_halt()
1359 			if (csr & MUSB_TXCSR_FIFONOTEMPTY) {  in musb_gadget_set_halt()
1372 		csr = musb_readw(epio, MUSB_TXCSR);  in musb_gadget_set_halt()
1373 		csr |= MUSB_TXCSR_P_WZC_BITS  in musb_gadget_set_halt()
1376 			csr |= MUSB_TXCSR_P_SENDSTALL;  in musb_gadget_set_halt()
1378 			csr &= ~(MUSB_TXCSR_P_SENDSTALL  in musb_gadget_set_halt()
1380 		csr &= ~MUSB_TXCSR_TXPKTRDY;  in musb_gadget_set_halt()
1381 		musb_writew(epio, MUSB_TXCSR, csr);  in musb_gadget_set_halt()
1383 		csr = musb_readw(epio, MUSB_RXCSR);  in musb_gadget_set_halt()
1384 		csr |= MUSB_RXCSR_P_WZC_BITS  in musb_gadget_set_halt()
1388 			csr |= MUSB_RXCSR_P_SENDSTALL;  in musb_gadget_set_halt()
1390 			csr &= ~(MUSB_RXCSR_P_SENDSTALL  in musb_gadget_set_halt()
1392 		musb_writew(epio, MUSB_RXCSR, csr);  in musb_gadget_set_halt()
1452 	u16		csr;  in musb_gadget_fifo_flush()  local
1463 		csr = musb_readw(epio, MUSB_TXCSR);  in musb_gadget_fifo_flush()
1464 		if (csr & MUSB_TXCSR_FIFONOTEMPTY) {  in musb_gadget_fifo_flush()
1465 			csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;  in musb_gadget_fifo_flush()
1471 			csr &= ~MUSB_TXCSR_TXPKTRDY;  in musb_gadget_fifo_flush()
1472 			musb_writew(epio, MUSB_TXCSR, csr);  in musb_gadget_fifo_flush()
1474 			musb_writew(epio, MUSB_TXCSR, csr);  in musb_gadget_fifo_flush()
1477 		csr = musb_readw(epio, MUSB_RXCSR);  in musb_gadget_fifo_flush()
1478 		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;  in musb_gadget_fifo_flush()
1479 		musb_writew(epio, MUSB_RXCSR, csr);  in musb_gadget_fifo_flush()
1480 		musb_writew(epio, MUSB_RXCSR, csr);  in musb_gadget_fifo_flush()