Lines Matching full:temp
258 u16 temp; in xhci_common_hub_descriptor() local
264 temp = 0; in xhci_common_hub_descriptor()
267 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
269 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
272 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
275 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
283 u16 temp; in xhci_usb2_hub_descriptor() local
293 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
294 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
660 u32 temp; in xhci_set_port_power() local
664 temp = readl(port->addr); in xhci_set_port_power()
667 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
669 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
673 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
677 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
681 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
683 if (temp) in xhci_set_port_power()
692 u32 temp; in xhci_port_set_test_mode() local
697 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
698 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
699 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
769 u32 temp; in xhci_set_link_state() local
773 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
774 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
775 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
776 writel(temp, port->addr); in xhci_set_link_state()
780 portsc, temp); in xhci_set_link_state()
786 u32 temp; in xhci_set_remote_wake_mask() local
788 temp = readl(port->addr); in xhci_set_remote_wake_mask()
789 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
792 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
794 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
797 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
799 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
802 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
804 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
806 writel(temp, port->addr); in xhci_set_remote_wake_mask()
813 u32 temp; in xhci_test_and_clear_bit() local
815 temp = readl(port->addr); in xhci_test_and_clear_bit()
816 if (temp & port_bit) { in xhci_test_and_clear_bit()
817 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
818 temp |= port_bit; in xhci_test_and_clear_bit()
819 writel(temp, port->addr); in xhci_test_and_clear_bit()
1182 u32 temp, status; in xhci_hub_control() local
1233 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1234 if (temp == ~(u32)0) { in xhci_hub_control()
1239 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1240 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1246 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1259 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1276 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1277 if (temp == ~(u32)0) { in xhci_hub_control()
1282 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1286 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1287 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1299 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1300 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1301 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1324 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1328 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1333 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1338 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1341 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1342 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1352 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1376 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1386 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1390 if (!(temp & PORT_PE)) { in xhci_hub_control()
1410 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1436 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1456 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1457 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1461 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1475 temp = (temp | PORT_RESET); in xhci_hub_control()
1476 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1478 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1480 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1485 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1487 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1490 temp |= PORT_WR; in xhci_hub_control()
1491 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1492 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1497 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1498 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1499 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1500 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1505 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1506 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1507 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1508 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1524 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1530 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1531 if (temp == ~(u32)0) { in xhci_hub_control()
1537 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1540 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1542 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1543 if (temp & PORT_RESET) in xhci_hub_control()
1545 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1546 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1582 ports[wIndex]->addr, temp); in xhci_hub_control()
1586 ports[wIndex]->addr, temp); in xhci_hub_control()
1618 u32 temp, status; in xhci_hub_status_data() local
1649 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1650 if (temp == ~(u32)0) { in xhci_hub_status_data()
1655 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1657 if ((temp & mask) != 0 || in xhci_hub_status_data()
1664 if ((temp & PORT_RC)) in xhci_hub_status_data()
1666 if (temp & PORT_OC) in xhci_hub_status_data()
1848 u32 temp, portsc; in xhci_bus_resume() local
1867 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1868 temp &= ~CMD_EIE; in xhci_bus_resume()
1869 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1946 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1947 temp |= CMD_EIE; in xhci_bus_resume()
1948 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1949 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()