1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (c) 2001-2002 by David Brownell
9 /* definitions used for the EHCI driver */
16  * To facilitate the strongest possible byte-order checking from "sparse"
46  * high-speed devices and full/low-speed devices lying behind a TT.
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92  * ehci-timer.c) in parallel with this list.
188 			the change-suspend feature turned on */
194 	/* per-HC memory pools (could be per-bus, but ...) */
233 	unsigned		has_ppcd:1; /* support per-port change bits */
258 	/* platform-specific data -- must come last */
265 	return (struct ehci_hcd *) (hcd->hcd_priv);  in hcd_to_ehci()
267 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)  in ehci_to_hcd()  argument
269 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);  in ehci_to_hcd()
272 /*-------------------------------------------------------------------------*/
274 #include <linux/usb/ehci_def.h>
276 /*-------------------------------------------------------------------------*/
278 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)  argument
281  * EHCI Specification 0.95 Section 3.5
283  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
289 	/* first part defined by EHCI spec */
290 	__hc32			hw_next;	/* see EHCI 3.5.1 */
291 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
292 	__hc32			hw_token;       /* see EHCI 3.5.3 */
307 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)  argument
308 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)  argument
309 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)  argument
311 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
314 	/* the rest is HCD-private */
321 /* mask NakCnt+T in qh->hw_alt_next */
322 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)  argument
326 /*-------------------------------------------------------------------------*/
328 /* type tag from {qh,itd,sitd,fstn}->hw_next */
329 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))  argument
335  * can be used on one system with SoC EHCI controller using big-endian
336  * descriptors as well as a normal little-endian PCI EHCI controller.
345 #define QH_NEXT(ehci, dma) \  argument
346 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
349 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */  argument
368 /*-------------------------------------------------------------------------*/
371  * EHCI Specification 0.95 Section 3.6
373  * See Fig 3-7 "Queue Head Structure Layout".
378 /* first part defined by EHCI spec */
380 	__hc32			hw_next;	/* see EHCI 3.6.1 */
381 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
389 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
395 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
407 	/* the rest is HCD-private */
439 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
444 /*-------------------------------------------------------------------------*/
449 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
450 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
457  * each packet is one logical usb transaction to the device (not TT),
458  * beginning at stream->next_uframe
468  * ehci_iso_stream - groups all (s)itds for this endpoint.
469  * acts like a qh would, if EHCI had them for ISO.
501 /*-------------------------------------------------------------------------*/
504  * EHCI Specification 0.95 Section 3.3
505  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
510 	/* first part defined by EHCI spec */
511 	__hc32			hw_next;           /* see EHCI 3.3.1 */
512 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
516 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
520 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)  argument
522 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
525 	/* the rest is HCD-private */
536 	unsigned		index[8];	/* in urb->iso_frame_desc */
539 /*-------------------------------------------------------------------------*/
542  * EHCI Specification 0.95 Section 3.4
543  * siTD, aka split-transaction isochronous Transfer Descriptor
545  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
548 	/* first part defined by EHCI spec */
550 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
551 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
552 	__hc32			hw_uframe;		/* EHCI table 3-10 */
553 	__hc32			hw_results;		/* EHCI table 3-11 */
565 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)  argument
567 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
568 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
571 	/* the rest is HCD-private */
582 /*-------------------------------------------------------------------------*/
585  * EHCI Specification 0.96 Section 3.7
597 	/* the rest is HCD-private */
602 /*-------------------------------------------------------------------------*/
605  * USB-2.0 Specification Sections 11.14 and 11.18
609  * port).  The bandwidth and budgeting information for the full/low-speed bus
610  * below each TT is self-contained and independent of the other TTs or the
611  * high-speed bus.
615  * the best-case estimate of the number of full-speed bytes allocated to an
619  * keep an up-to-date record, we recompute the budget when it is needed.
631 /*-------------------------------------------------------------------------*/
635 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\  argument
636 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
638 #define ehci_prepare_ports_for_controller_resume(ehci)			\  argument
639 		ehci_adjust_port_wakeup_flags(ehci, false, false)
641 /*-------------------------------------------------------------------------*/
646  * Some EHCI controllers have a Transaction Translator built into the
647  * root hub. This is a non-standard feature.  Each controller will need
652 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
656 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)  in ehci_port_speed()  argument
658 	if (ehci_is_TDI(ehci)) {  in ehci_port_speed()
659 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
676 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED  argument
679 /*-------------------------------------------------------------------------*/
683  * port number in the queue head was 0..N-1 instead of 1..N.
685 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
690 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
693 /* Some Freescale processors have an erratum (USB A-005275) in which
696 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
702  * Some Freescale/NXP processors have an erratum (USB A-005697)
706 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
709  * While most USB host controllers implement their registers in
710  * little-endian format, a minority (celleb companion chip) implement
719  * as fields of a 32-bit register.
723 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
724 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
731  * Big-endian read/write functions are arch-specific.
739 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,  in ehci_readl()  argument
743 	return ehci_big_endian_mmio(ehci) ?  in ehci_readl()
763 static inline void ehci_writel(const struct ehci_hcd *ehci,  in ehci_writel()  argument
767 	ehci_big_endian_mmio(ehci) ?  in ehci_writel()
771 	if (ehci->imx28_write_fix)  in ehci_writel()
779  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
784 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
788 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
794 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
795 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
798 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
802 /*-------------------------------------------------------------------------*/
805  * The AMCC 440EPx not only implements its EHCI registers in big-endian
808  * EHCI controllers accessed through PCI work normally (little-endian
809  * everywhere), so we won't bother supporting a BE-only mode for now.
812 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
814 /* cpu to ehci */
815 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
817 	return ehci_big_endian_desc(ehci)  in cpu_to_hc32()
822 /* ehci to cpu */
823 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
825 	return ehci_big_endian_desc(ehci)  in hc32_to_cpu()
830 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
832 	return ehci_big_endian_desc(ehci)  in hc32_to_cpup()
839 /* cpu to ehci */
840 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
845 /* ehci to cpu */
846 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
851 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
858 /*-------------------------------------------------------------------------*/
860 #define ehci_dbg(ehci, fmt, args...) \  argument
861 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
862 #define ehci_err(ehci, fmt, args...) \  argument
863 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
864 #define ehci_info(ehci, fmt, args...) \  argument
865 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866 #define ehci_warn(ehci, fmt, args...) \  argument
867 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
869 /*-------------------------------------------------------------------------*/
871 /* Declarations of things exported for use by ehci platform drivers */
883 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
885 extern int	ehci_reset(struct ehci_hcd *ehci);
889 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,