Lines Matching +full:rs485 +full:- +full:rx +full:- +full:during +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
15 #include <linux/dma-direction.h>
17 #include <linux/dma-mapping.h>
36 #include "stm32-usart.h"
50 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
52 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
59 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
61 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
110 port->rs485 = *rs485conf; in stm32_usart_config_rs485()
112 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
114 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
115 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
116 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
117 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
127 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
128 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_config_rs485()
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
139 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
140 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
142 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
144 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
156 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
158 rs485conf->flags = 0; in stm32_usart_init_rs485()
159 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
160 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
162 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
163 return -ENODEV; in stm32_usart_init_rs485()
172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx()
176 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx()
178 if (threaded && stm32_port->rx_ch) { in stm32_usart_pending_rx()
179 status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_pending_rx()
180 stm32_port->rx_ch->cookie, in stm32_usart_pending_rx()
196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char()
199 if (stm32_port->rx_ch) { in stm32_usart_get_char()
200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; in stm32_usart_get_char()
204 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char()
206 c &= stm32_port->rdr_mask; in stm32_usart_get_char()
214 struct tty_port *tport = &port->state->port; in stm32_usart_receive_chars()
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
221 spin_lock(&port->lock); in stm32_usart_receive_chars()
223 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, in stm32_usart_receive_chars()
233 * and clear status bits of the next rx data. in stm32_usart_receive_chars()
237 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars()
239 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars()
241 port->membase + ofs->icr); in stm32_usart_receive_chars()
243 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); in stm32_usart_receive_chars()
244 port->icount.rx++; in stm32_usart_receive_chars()
247 port->icount.overrun++; in stm32_usart_receive_chars()
249 port->icount.parity++; in stm32_usart_receive_chars()
253 port->icount.brk++; in stm32_usart_receive_chars()
257 port->icount.frame++; in stm32_usart_receive_chars()
261 sr &= port->read_status_mask; in stm32_usart_receive_chars()
287 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_tx_dma_complete()
290 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_tx_dma_complete()
291 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_tx_dma_complete()
292 stm32port->tx_dma_busy = false; in stm32_usart_tx_dma_complete()
295 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
297 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
306 * Enables TX FIFO threashold irq when FIFO is enabled, in stm32_usart_tx_interrupt_enable()
307 * or TX empty irq when FIFO is disabled in stm32_usart_tx_interrupt_enable()
309 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
310 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
312 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
318 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
320 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
321 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
323 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
329 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
330 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
332 if (stm32_port->tx_dma_busy) { in stm32_usart_transmit_chars_pio()
333 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_pio()
334 stm32_port->tx_dma_busy = false; in stm32_usart_transmit_chars_pio()
339 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
341 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_pio()
343 port->icount.tx++; in stm32_usart_transmit_chars_pio()
356 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_transmit_chars_dma()
357 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
361 if (stm32port->tx_dma_busy) in stm32_usart_transmit_chars_dma()
364 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
371 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
374 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
379 two = count - one; in stm32_usart_transmit_chars_dma()
381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
386 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
387 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
395 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
396 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
398 /* Push current DMA TX transaction in the pending queue */ in stm32_usart_transmit_chars_dma()
401 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
405 /* Issue pending DMA TX requests */ in stm32_usart_transmit_chars_dma()
406 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
408 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
410 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_dma()
411 port->icount.tx += count; in stm32_usart_transmit_chars_dma()
415 for (i = count; i > 0; i--) in stm32_usart_transmit_chars_dma()
422 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
423 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
425 if (port->x_char) { in stm32_usart_transmit_chars()
426 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
427 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
428 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
429 port->x_char = 0; in stm32_usart_transmit_chars()
430 port->icount.tx++; in stm32_usart_transmit_chars()
431 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
432 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
441 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
442 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
444 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
446 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
461 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
463 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
466 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
468 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
470 port->membase + ofs->icr); in stm32_usart_interrupt()
472 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
475 port->membase + ofs->icr); in stm32_usart_interrupt()
476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
477 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
478 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
481 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) in stm32_usart_interrupt()
484 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
485 spin_lock(&port->lock); in stm32_usart_interrupt()
487 spin_unlock(&port->lock); in stm32_usart_interrupt()
490 if (stm32_port->rx_ch) in stm32_usart_interrupt()
501 if (stm32_port->rx_ch) in stm32_usart_threaded_interrupt()
510 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
512 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
521 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
523 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
524 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
528 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
539 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
544 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
549 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
556 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_stop_tx()
560 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_stop_tx()
561 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_stop_tx()
562 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
563 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_stop_tx()
565 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
566 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_stop_tx()
575 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_start_tx()
576 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
581 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_start_tx()
582 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_start_tx()
583 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
584 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_start_tx()
586 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
587 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_start_tx()
598 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_flush_buffer()
600 if (stm32_port->tx_ch) { in stm32_usart_flush_buffer()
601 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_flush_buffer()
602 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_flush_buffer()
603 stm32_port->tx_dma_busy = false; in stm32_usart_flush_buffer()
611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
614 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
616 if (stm32_port->cr3_irq) in stm32_usart_throttle()
617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
619 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
629 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
631 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
634 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
644 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
648 /* Handle breaks - ignored by us */
656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
658 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
669 if (stm32_port->swap) { in stm32_usart_startup()
670 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
672 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
675 /* RX FIFO Flush */ in stm32_usart_startup()
676 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
677 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
679 /* RX enabling */ in stm32_usart_startup()
680 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
681 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
689 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
690 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
698 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
699 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
700 if (stm32_port->fifoen) in stm32_usart_shutdown()
703 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
709 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
711 /* flush RX & TX FIFO */ in stm32_usart_shutdown()
712 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
714 port->membase + ofs->rqr); in stm32_usart_shutdown()
716 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
718 free_irq(port->irq, port); in stm32_usart_shutdown()
726 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
727 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
728 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
731 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
736 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
739 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
741 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
743 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
750 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
753 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
755 /* flush RX & TX FIFO */ in stm32_usart_set_termios()
756 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
758 port->membase + ofs->rqr); in stm32_usart_set_termios()
761 if (stm32_port->fifoen) in stm32_usart_set_termios()
763 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
765 /* Tx and RX FIFO configuration */ in stm32_usart_set_termios()
766 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
768 if (stm32_port->fifoen) { in stm32_usart_set_termios()
769 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
770 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
771 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
772 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
779 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
795 else if ((bits == 7) && cfg->has_7bits_data) in stm32_usart_set_termios()
798 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
801 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
802 (stm32_port->fifoen && in stm32_usart_set_termios()
803 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
809 /* RX timeout irq to occur after last stop bit + bits */ in stm32_usart_set_termios()
810 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
811 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
814 if (!stm32_port->rx_ch) in stm32_usart_set_termios()
815 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
818 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
819 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
824 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
826 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
830 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
841 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
845 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
850 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
854 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
855 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
856 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
857 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
858 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
861 port->ignore_status_mask = 0; in stm32_usart_set_termios()
862 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
863 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
864 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
865 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
870 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
871 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
875 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
876 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
878 if (stm32_port->rx_ch) in stm32_usart_set_termios()
881 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
883 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
884 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
886 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
888 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
891 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
900 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
905 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
906 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
907 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
909 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
910 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
913 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
921 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
936 port->type = PORT_STM32; in stm32_usart_config_port()
943 return -EINVAL; in stm32_usart_verify_port()
951 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
952 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
957 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
960 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
961 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
962 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
963 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
992 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1004 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ in stm32_usart_get_ftcfg()
1005 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1012 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1014 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, in stm32_usart_get_ftcfg()
1019 *ftcfg = i - 1; in stm32_usart_get_ftcfg()
1021 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1026 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1032 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1040 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1041 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1042 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1043 port->dev = &pdev->dev; in stm32_usart_init_port()
1044 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1045 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1046 port->irq = irq; in stm32_usart_init_port()
1047 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1053 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1054 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1056 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1057 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1059 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1060 if (stm32port->fifoen) { in stm32_usart_init_port()
1061 stm32_usart_get_ftcfg(pdev, "rx-threshold", in stm32_usart_init_port()
1062 &stm32port->rxftcfg); in stm32_usart_init_port()
1063 stm32_usart_get_ftcfg(pdev, "tx-threshold", in stm32_usart_init_port()
1064 &stm32port->txftcfg); in stm32_usart_init_port()
1067 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1068 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1069 return PTR_ERR(port->membase); in stm32_usart_init_port()
1070 port->mapbase = res->start; in stm32_usart_init_port()
1072 spin_lock_init(&port->lock); in stm32_usart_init_port()
1074 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1075 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1076 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1079 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1083 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1084 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1085 ret = -EINVAL; in stm32_usart_init_port()
1089 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1090 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1091 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1096 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1099 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1100 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1101 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1102 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1103 ret = -EINVAL; in stm32_usart_init_port()
1111 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1118 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1126 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1134 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1135 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1145 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1146 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1147 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1157 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1158 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1159 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1165 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1166 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1167 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1177 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1179 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1180 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1182 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1183 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1187 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1190 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1192 dev_err(dev, "rx dma channel config failed\n"); in stm32_usart_of_dma_rx_probe()
1198 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, in stm32_usart_of_dma_rx_probe()
1199 stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1203 dev_err(dev, "rx dma prep cyclic failed\n"); in stm32_usart_of_dma_rx_probe()
1205 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1209 desc->callback = NULL; in stm32_usart_of_dma_rx_probe()
1210 desc->callback_param = NULL; in stm32_usart_of_dma_rx_probe()
1215 dmaengine_terminate_sync(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1221 dma_async_issue_pending(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1229 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1230 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1231 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1237 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1238 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1239 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1243 stm32port->tx_dma_busy = false; in stm32_usart_of_dma_tx_probe()
1245 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1246 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1248 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1249 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1253 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1256 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1258 dev_err(dev, "tx dma channel config failed\n"); in stm32_usart_of_dma_tx_probe()
1273 return -ENODEV; in stm32_usart_serial_probe()
1275 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1276 if (!stm32port->info) in stm32_usart_serial_probe()
1277 return -EINVAL; in stm32_usart_serial_probe()
1283 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1284 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1285 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1290 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1291 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1292 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1295 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1296 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1297 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1299 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1300 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1301 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1304 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1305 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1306 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1308 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1310 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1311 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1314 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1316 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1317 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1320 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1321 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1322 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1323 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1325 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1327 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1328 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1329 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1331 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1335 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1340 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1341 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1342 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1344 if (stm32port->tx_ch) { in stm32_usart_serial_probe()
1346 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1349 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1353 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1354 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1357 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1358 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1361 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1362 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1373 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1376 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1381 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1382 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1383 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1385 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_serial_remove()
1387 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1388 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_serial_remove()
1390 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1393 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1394 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_serial_remove()
1396 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1399 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_serial_remove()
1401 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1402 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1403 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1415 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1417 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_console_putchar()
1420 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1426 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1429 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1435 locked = spin_trylock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1437 spin_lock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1440 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1442 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1443 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1448 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1451 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_console_write()
1462 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1463 return -ENODEV; in stm32_usart_console_setup()
1465 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1470 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1473 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1474 return -ENXIO; in stm32_usart_console_setup()
1479 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1488 .index = -1,
1511 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
1513 if (!stm32_port->wakeup_src) in stm32_usart_serial_en_wakeup()
1517 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
1518 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
1521 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1522 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1524 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1525 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1572 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
1583 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()