Lines Matching full:sifive

3  * SiFive UART driver
5  * Copyright (C) 2018-2019 SiFive
22  * - drivers/pwm/pwm-sifive.c
26  *   SiFive FE310-G000 v2p3
28  *   https://github.com/sifive/sifive-blocks/
30  * The SiFive UART design is not 8250-compatible.  The following common
127 #define SIFIVE_SERIAL_NAME			"sifive-serial"
129 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
156  * Configuration data specific to this SiFive UART.
190  * __ssp_early_writel() - write to a SiFive serial port register (early)
207  * __ssp_early_readl() - read from a SiFive serial port register (early)
227  * __ssp_writel() - write to a SiFive serial port register
243  * __ssp_readl() - read from a SiFive serial port register
297  * transmit buffer to the SiFive UART TX FIFO.
337  * on the SiFive UART referred to by @ssp.
353  * on the SiFive UART referred to by @ssp.
401  * Try to read a byte from the SiFive UART RX FIFO, referenced by
431  * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
477  * SiFive UART described by @ssp and program it into the UART.  There may
496  * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
728 	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;  in sifive_serial_type()
790 OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
791 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
1055 	{ .compatible = "sifive,fu540-c000-uart0" },
1056 	{ .compatible = "sifive,uart0" },
1099 MODULE_DESCRIPTION("SiFive UART serial driver");