Lines Matching +full:clock +full:- +full:error +full:- +full:detect
1 /* SPDX-License-Identifier: GPL-2.0 */
31 SCCKS, /* BRG Clock Select Register */
42 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
43 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
44 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
48 #define SCSMR_CKS 0x0003 /* Clock Select */
51 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
66 /* Serial Control Register, HSCIF-only bits */
72 #define SCI_ORER BIT(5) /* Overrun Error */
73 #define SCI_FER BIT(4) /* Framing Error */
74 #define SCI_PER BIT(3) /* Parity Error */
86 #define SCIF_ER BIT(7) /* Receive Error */
89 #define SCIF_BRK BIT(4) /* Break Detect */
90 #define SCIF_FER BIT(3) /* Framing Error */
91 #define SCIF_PER BIT(2) /* Parity Error */
98 #define SCIFA_ORER BIT(9) /* Overrun Error */
119 #define SCLSR_ORER BIT(0) /* Overrun Error */
126 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
127 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
153 * BRG Clock Select Register (Some SCIF and HSCIF)
154 * The Baud Rate Generator for external clock can provide a clock source for
155 * the sampling clock. It outputs either its frequency divided clock, or the
156 * (undivided) (H)SCK external clock.
159 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
161 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
162 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
163 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
168 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
171 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
173 (to_sci_port(port)->params->error_clear)
175 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
177 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)