Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
57 * Tx fifo trigger level setting in tegra uart is in
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
84 * @fifo_mode_enable_status: Is FIFO mode enabled?
160 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
166 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
179 * RI - Ring detector is active in tegra_uart_get_mctrl()
180 * CD/DCD/CAR - Carrier detect is always active. For some reason in tegra_uart_get_mctrl()
182 * DSR - Data Set ready is active as the hardware doesn't support it. in tegra_uart_get_mctrl()
184 * CTS - Clear to send. Always set to active, as the hardware handles in tegra_uart_get_mctrl()
187 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
196 mcr = tup->mcr_shadow; in set_rts()
201 if (mcr != tup->mcr_shadow) { in set_rts()
203 tup->mcr_shadow = mcr; in set_rts()
211 mcr = tup->mcr_shadow; in set_dtr()
216 if (mcr != tup->mcr_shadow) { in set_dtr()
218 tup->mcr_shadow = mcr; in set_dtr()
224 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
231 if (mcr != tup->mcr_shadow) { in set_loopbk()
233 tup->mcr_shadow = mcr; in set_loopbk()
242 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
243 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
257 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
263 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
278 if (tup->current_baud) in tegra_uart_wait_cycle_time()
279 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
282 /* Wait for a symbol-time. */
286 if (tup->current_baud) in tegra_uart_wait_sym_time()
287 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
288 tup->current_baud)); in tegra_uart_wait_sym_time()
301 } while (--tmout); in tegra_uart_wait_fifo_mode_enabled()
303 return -ETIMEDOUT; in tegra_uart_wait_fifo_mode_enabled()
308 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
311 if (tup->rts_active) in tegra_uart_fifo_reset()
314 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
325 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
344 } while (--tmout); in tegra_uart_fifo_reset()
346 if (tup->rts_active) in tegra_uart_fifo_reset()
355 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
356 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
357 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
359 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
369 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
370 / tup->required_rate; in tegra_check_rate_in_range()
371 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
372 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
373 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
375 return -EIO; in tegra_check_rate_in_range()
389 if (tup->current_baud == baud) in tegra_set_baudrate()
392 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
394 tup->required_rate = rate; in tegra_set_baudrate()
396 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
399 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
401 dev_err(tup->uport.dev, in tegra_set_baudrate()
405 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
411 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
415 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_set_baudrate()
416 lcr = tup->lcr_shadow; in tegra_set_baudrate()
428 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_set_baudrate()
430 tup->current_baud = baud; in tegra_set_baudrate()
446 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
447 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
451 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
452 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
455 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
456 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
460 * If FIFO read error without any data, reset Rx FIFO in tegra_uart_decode_rx_error()
464 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
467 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
468 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
470 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
488 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
493 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
498 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
499 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in tegra_uart_fill_tx_fifo()
500 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
510 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
511 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
512 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
513 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
519 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
524 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
525 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
526 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
527 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
528 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in tegra_uart_tx_dma_complete()
529 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
531 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
533 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
539 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
542 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
543 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
545 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
546 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
548 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
549 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
551 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
552 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
553 return -EIO; in tegra_uart_start_tx_dma()
556 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
557 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
558 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
559 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
560 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
561 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
569 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
571 if (!tup->current_baud) in tegra_uart_start_next_tx()
574 tail = (unsigned long)&xmit->buf[xmit->tail]; in tegra_uart_start_next_tx()
575 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in tegra_uart_start_next_tx()
579 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
587 /* Called by serial core driver with u->lock taken. */
591 struct circ_buf *xmit = &u->state->xmit; in tegra_uart_start_tx()
593 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
603 spin_lock_irqsave(&u->lock, flags); in tegra_uart_tx_empty()
604 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
609 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_tx_empty()
616 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_stop_tx()
620 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
623 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
624 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
625 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
626 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
627 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in tegra_uart_stop_tx()
628 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
633 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
635 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
636 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
638 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
659 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
661 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
664 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
681 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
683 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
686 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
689 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
692 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
694 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
700 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
701 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
713 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
716 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
717 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
728 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
733 spin_lock_irqsave(&u->lock, flags); in tegra_uart_rx_dma_complete()
735 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
738 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
743 if (tup->rts_active) in tegra_uart_rx_dma_complete()
746 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
751 if (tup->rts_active) in tegra_uart_rx_dma_complete()
755 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_rx_dma_complete()
762 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
767 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
768 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
771 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
777 if (tup->rts_active) in tegra_uart_handle_rx_dma()
782 if (tup->rts_active) in tegra_uart_handle_rx_dma()
790 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
793 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
794 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
796 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
797 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
798 return -EIO; in tegra_uart_start_rx_dma()
801 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
802 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
803 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
804 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
805 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
806 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
820 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
822 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
825 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
828 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
834 struct uart_port *u = &tup->uport; in tegra_uart_isr()
841 spin_lock_irqsave(&u->lock, flags); in tegra_uart_isr()
845 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
847 if (tup->rx_in_progress) { in tegra_uart_isr()
848 ier = tup->ier_shadow; in tegra_uart_isr()
851 tup->ier_shadow = ier; in tegra_uart_isr()
857 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_isr()
867 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
868 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
874 if (!tup->use_rx_pio) { in tegra_uart_isr()
875 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
877 ier = tup->ier_shadow; in tegra_uart_isr()
880 tup->ier_shadow = ier; in tegra_uart_isr()
886 if (!tup->use_rx_pio) { in tegra_uart_isr()
887 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
888 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
889 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
911 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
914 if (tup->rts_active) in tegra_uart_stop_rx()
917 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
922 ier = tup->ier_shadow; in tegra_uart_stop_rx()
925 tup->ier_shadow = ier; in tegra_uart_stop_rx()
927 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
929 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
938 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
939 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
953 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
954 "Tx Fifo not empty, CTS disabled, waiting\n"); in tegra_uart_hw_deinit()
956 /* Wait for Tx fifo to be empty */ in tegra_uart_hw_deinit()
960 fifo_empty_time -= wait_time; in tegra_uart_hw_deinit()
966 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
974 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
977 tup->current_baud = 0; in tegra_uart_hw_deinit()
978 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
980 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
981 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
983 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
985 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
988 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
995 tup->fcr_shadow = 0; in tegra_uart_hw_init()
996 tup->mcr_shadow = 0; in tegra_uart_hw_init()
997 tup->lcr_shadow = 0; in tegra_uart_hw_init()
998 tup->ier_shadow = 0; in tegra_uart_hw_init()
999 tup->current_baud = 0; in tegra_uart_hw_init()
1001 clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
1004 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1006 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1008 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1009 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1018 * interrupt is received. Rx high watermark is set to 4. in tegra_uart_hw_init()
1021 * interrupt the CPU when the number of entries in the FIFO reaches the in tegra_uart_hw_init()
1022 * low watermark. Tx low watermark is set to 16 bytes. in tegra_uart_hw_init()
1029 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1031 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1032 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1034 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1035 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1040 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1041 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1046 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1049 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1050 "Failed to enable FIFO mode: %d\n", ret); in tegra_uart_hw_init()
1057 * periods after enabling the TX fifo, otherwise data could in tegra_uart_hw_init()
1070 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1073 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1074 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1075 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1076 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1078 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1080 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1086 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when in tegra_uart_hw_init()
1087 * the DATA is sitting in the FIFO and couldn't be transferred to the in tegra_uart_hw_init()
1092 * For pauses in the data which is not aligned to 4 bytes, we get in tegra_uart_hw_init()
1093 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first in tegra_uart_hw_init()
1096 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1102 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1103 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1105 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1113 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1114 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1115 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1116 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1117 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1118 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1119 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1121 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1122 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1123 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1125 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1126 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1127 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1140 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1143 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1149 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1153 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1156 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1158 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1161 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1163 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1164 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1165 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1166 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1168 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1169 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
1171 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1172 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1174 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1176 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
1177 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1180 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1181 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1182 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1187 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1201 if (!tup->use_tx_pio) { in tegra_uart_startup()
1204 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1210 if (!tup->use_rx_pio) { in tegra_uart_startup()
1213 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1221 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); in tegra_uart_startup()
1225 ret = request_irq(u->irq, tegra_uart_isr, 0, in tegra_uart_startup()
1226 dev_name(u->dev), tup); in tegra_uart_startup()
1228 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); in tegra_uart_startup()
1234 if (!tup->use_rx_pio) in tegra_uart_startup()
1237 if (!tup->use_tx_pio) in tegra_uart_startup()
1250 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1251 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1252 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1260 free_irq(u->irq, tup); in tegra_uart_shutdown()
1267 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1268 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1269 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1281 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1283 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1287 spin_lock_irqsave(&u->lock, flags); in tegra_uart_set_termios()
1290 if (tup->rts_active) in tegra_uart_set_termios()
1294 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1300 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1304 termios->c_cflag &= ~CMSPAR; in tegra_uart_set_termios()
1306 if ((termios->c_cflag & PARENB) == PARENB) { in tegra_uart_set_termios()
1308 if (termios->c_cflag & PARODD) { in tegra_uart_set_termios()
1320 switch (termios->c_cflag & CSIZE) { in tegra_uart_set_termios()
1340 if (termios->c_cflag & CSTOPB) { in tegra_uart_set_termios()
1349 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1350 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1356 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_set_termios()
1359 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1364 spin_lock_irqsave(&u->lock, flags); in tegra_uart_set_termios()
1367 if (termios->c_cflag & CRTSCTS) { in tegra_uart_set_termios()
1368 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1372 if (tup->rts_active) in tegra_uart_set_termios()
1375 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1376 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1377 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1381 uart_update_timeout(u, termios->c_cflag, baud); in tegra_uart_set_termios()
1386 /* Re-enable interrupt */ in tegra_uart_set_termios()
1387 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1390 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1392 if ((termios->c_cflag & CREAD) == 0) in tegra_uart_set_termios()
1393 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1394 if (termios->c_iflag & IGNBRK) in tegra_uart_set_termios()
1395 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1397 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_set_termios()
1434 struct device_node *np = pdev->dev.of_node; in tegra_uart_parse_dt()
1444 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); in tegra_uart_parse_dt()
1447 tup->uport.line = port; in tegra_uart_parse_dt()
1449 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1450 "nvidia,enable-modem-interrupt"); in tegra_uart_parse_dt()
1452 index = of_property_match_string(np, "dma-names", "rx"); in tegra_uart_parse_dt()
1454 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1455 dev_info(&pdev->dev, "RX in PIO mode\n"); in tegra_uart_parse_dt()
1457 index = of_property_match_string(np, "dma-names", "tx"); in tegra_uart_parse_dt()
1459 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1460 dev_info(&pdev->dev, "TX in PIO mode\n"); in tegra_uart_parse_dt()
1463 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); in tegra_uart_parse_dt()
1465 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1466 tup->baud_tolerance = in tegra_uart_parse_dt()
1467 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1468 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1469 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1470 return -ENOMEM; in tegra_uart_parse_dt()
1475 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1478 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1482 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1485 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1489 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1492 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1496 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1542 .error_tolerance_low_range = -2,
1548 .compatible = "nvidia,tegra30-hsuart",
1551 .compatible = "nvidia,tegra20-hsuart",
1554 .compatible = "nvidia,tegra186-hsuart",
1557 .compatible = "nvidia,tegra194-hsuart",
1572 cdata = of_device_get_match_data(&pdev->dev); in tegra_uart_probe()
1574 dev_err(&pdev->dev, "Error: No device match found\n"); in tegra_uart_probe()
1575 return -ENODEV; in tegra_uart_probe()
1578 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1580 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); in tegra_uart_probe()
1581 return -ENOMEM; in tegra_uart_probe()
1588 u = &tup->uport; in tegra_uart_probe()
1589 u->dev = &pdev->dev; in tegra_uart_probe()
1590 u->ops = &tegra_uart_ops; in tegra_uart_probe()
1591 u->type = PORT_TEGRA; in tegra_uart_probe()
1592 u->fifosize = 32; in tegra_uart_probe()
1593 tup->cdata = cdata; in tegra_uart_probe()
1598 dev_err(&pdev->dev, "No IO memory resource\n"); in tegra_uart_probe()
1599 return -ENODEV; in tegra_uart_probe()
1602 u->mapbase = resource->start; in tegra_uart_probe()
1603 u->membase = devm_ioremap_resource(&pdev->dev, resource); in tegra_uart_probe()
1604 if (IS_ERR(u->membase)) in tegra_uart_probe()
1605 return PTR_ERR(u->membase); in tegra_uart_probe()
1607 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1608 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1609 dev_err(&pdev->dev, "Couldn't get the clock\n"); in tegra_uart_probe()
1610 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1613 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1614 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1615 dev_err(&pdev->dev, "Couldn't get the reset\n"); in tegra_uart_probe()
1616 return PTR_ERR(tup->rst); in tegra_uart_probe()
1619 u->iotype = UPIO_MEM32; in tegra_uart_probe()
1623 u->irq = ret; in tegra_uart_probe()
1624 u->regshift = 2; in tegra_uart_probe()
1627 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); in tegra_uart_probe()
1636 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1646 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1654 struct uart_port *u = &tup->uport; in tegra_uart_resume()
1668 .name = "serial-tegra",
1685 cdata = match->data; in tegra_uart_init()
1687 tegra_uart_driver.nr = cdata->uart_max_port; in tegra_uart_init()
1715 MODULE_ALIAS("platform:serial-tegra");