16 #include <linux/qcom-geni-se.h>
122 	struct geni_se se;  member
205 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
493 		geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_console_write()
496 			geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_console_write()
629 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx()
632 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx()
650 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_start_rx()
681 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx()
874 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);  in get_tx_fifo_size()
875 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);  in get_tx_fifo_size()
876 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);  in get_tx_fifo_size()
894 	proto = geni_se_read_proto(&port->se);  in qcom_geni_serial_port_setup()
925 	geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_port_setup()
927 	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);  in qcom_geni_serial_port_setup()
928 	geni_se_select_mode(&port->se, GENI_SE_FIFO);  in qcom_geni_serial_port_setup()
1002 	ver = geni_se_get_qup_hw_version(&port->se);  in qcom_geni_serial_set_termios()
1021 	port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;  in qcom_geni_serial_set_termios()
1022 	port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);  in qcom_geni_serial_set_termios()
1023 	geni_icc_set_bw(&port->se);  in qcom_geni_serial_set_termios()
1155 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1158 	geni_se_setup_s_cmd(se, UART_START_READ, 0);  in qcom_geni_serial_enable_early_read()
1162 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1178 	struct geni_se se;  in qcom_geni_serial_earlycon_setup()  local
1185 	memset(&se, 0, sizeof(se));  in qcom_geni_serial_earlycon_setup()
1186 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1187 	if (geni_se_read_proto(&se) != GENI_SE_UART)  in qcom_geni_serial_earlycon_setup()
1202 	geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_earlycon_setup()
1204 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);  in qcom_geni_serial_earlycon_setup()
1205 	geni_se_select_mode(&se, GENI_SE_FIFO);  in qcom_geni_serial_earlycon_setup()
1217 	qcom_geni_serial_enable_early_read(&se, dev->con);  in qcom_geni_serial_earlycon_setup()
1279 		geni_icc_enable(&port->se);  in qcom_geni_serial_pm()
1280 		geni_se_resources_on(&port->se);  in qcom_geni_serial_pm()
1283 		geni_se_resources_off(&port->se);  in qcom_geni_serial_pm()
1284 		geni_icc_disable(&port->se);  in qcom_geni_serial_pm()
1360 	port->se.dev = &pdev->dev;  in qcom_geni_serial_probe()
1361 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);  in qcom_geni_serial_probe()
1362 	port->se.clk = devm_clk_get(&pdev->dev, "se");  in qcom_geni_serial_probe()
1363 	if (IS_ERR(port->se.clk)) {  in qcom_geni_serial_probe()
1364 		ret = PTR_ERR(port->se.clk);  in qcom_geni_serial_probe()
1365 		dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);  in qcom_geni_serial_probe()
1385 	ret = geni_icc_get(&port->se, NULL);  in qcom_geni_serial_probe()
1388 	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1389 	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1392 	ret = geni_icc_set_bw(&port->se);  in qcom_geni_serial_probe()
1417 	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");  in qcom_geni_serial_probe()
1489 		geni_icc_set_tag(&port->se, 0x3);  in qcom_geni_serial_sys_suspend()
1490 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_suspend()
1504 		geni_icc_set_tag(&port->se, 0x7);  in qcom_geni_serial_sys_resume()
1505 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_resume()