Lines Matching +full:ext +full:- +full:reset +full:- +full:output
1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
111 (void)readb(port->control_reg); in zssync()
118 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
147 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
149 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
150 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
151 #define ERR_RES 0x30 /* Error Reset */
152 #define RES_H_IUS 0x38 /* Reset highest IUS */
154 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
155 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
156 #define RES_EOM_L 0xC0 /* Reset EOM latch */
160 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
216 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
226 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
228 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
241 #define NORESET 0 /* No reset on write to R9 */
242 #define CHRB 0x40 /* Reset channel B */
243 #define CHRA 0x80 /* Reset channel A */
244 #define FHWRES 0xc0 /* Force hardware reset */
259 #define TRxCXT 0 /* TRxC = Xtal output */
261 #define TRxCBR 2 /* TRxC = BR Generator Output */
262 #define TRxCDP 3 /* TRxC = DPLL output */
266 #define TCBR 0x10 /* Transmit clock = BR Generator output */
267 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
270 #define RCBR 0x40 /* Receive clock = BR Generator output */
271 #define RCDPLL 0x60 /* Receive clock = DPLL output */
285 #define RMC 0x40 /* Reset missing clock */
293 #define EN85C30 1 /* Enable some 85c30-enhanced registers */
330 /* Read Register 2 (channel b only) - Interrupt vector */
342 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
345 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
371 #define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
372 #define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
373 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
374 #define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
375 #define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
376 #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
377 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
378 #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
379 #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
380 #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
381 #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
382 #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)