Lines Matching +full:uart +full:- +full:fifosize
1 // SPDX-License-Identifier: GPL-2.0
36 /* Set the max number of UART port
247 * struct pch_uart_driver_data - private data structure for UART-DMA
248 * @port_type: The type of UART port
249 * @line_no: UART port line number (0, 1, 2...)
300 struct eg20t_port *priv = file->private_data; in port_show_regs()
310 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
311 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
316 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
318 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
320 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
322 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
324 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
325 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
326 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
327 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
329 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
331 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
332 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
333 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
334 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); in port_show_regs()
335 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
336 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); in port_show_regs()
337 iowrite8(lcr, priv->membase + UART_LCR); in port_show_regs()
356 .ident = "CM-iTC",
358 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
377 .ident = "COMe-mTT",
379 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
384 .ident = "nanoETXexpress-TT",
386 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
400 /* Return UART clock, checking for board specific clocks. */
410 return (unsigned long)d->driver_data; in pch_uart_get_uartclk()
418 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
420 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
426 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
428 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
438 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); in pch_uart_hal_set_line()
440 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); in pch_uart_hal_set_line()
441 return -EINVAL; in pch_uart_hal_set_line()
448 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); in pch_uart_hal_set_line()
449 return -EINVAL; in pch_uart_hal_set_line()
453 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); in pch_uart_hal_set_line()
454 return -EINVAL; in pch_uart_hal_set_line()
458 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); in pch_uart_hal_set_line()
459 return -EINVAL; in pch_uart_hal_set_line()
466 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", in pch_uart_hal_set_line()
468 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in pch_uart_hal_set_line()
469 iowrite8(dll, priv->membase + PCH_UART_DLL); in pch_uart_hal_set_line()
470 iowrite8(dlm, priv->membase + PCH_UART_DLM); in pch_uart_hal_set_line()
471 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_line()
480 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", in pch_uart_hal_fifo_reset()
482 return -EINVAL; in pch_uart_hal_fifo_reset()
485 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
486 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, in pch_uart_hal_fifo_reset()
487 priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
488 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
500 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", in pch_uart_hal_set_fifo()
502 return -EINVAL; in pch_uart_hal_set_fifo()
506 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", in pch_uart_hal_set_fifo()
508 return -EINVAL; in pch_uart_hal_set_fifo()
512 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", in pch_uart_hal_set_fifo()
514 return -EINVAL; in pch_uart_hal_set_fifo()
517 switch (priv->fifo_size) { in pch_uart_hal_set_fifo()
519 priv->trigger_level = in pch_uart_hal_set_fifo()
523 priv->trigger_level = in pch_uart_hal_set_fifo()
527 priv->trigger_level = in pch_uart_hal_set_fifo()
531 priv->trigger_level = in pch_uart_hal_set_fifo()
537 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
539 priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
540 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
541 priv->fcr = fcr; in pch_uart_hal_set_fifo()
548 unsigned int msr = ioread8(priv->membase + UART_MSR); in pch_uart_hal_get_modem()
549 priv->dmsr = msr & PCH_UART_MSR_DELTA; in pch_uart_hal_get_modem()
561 iowrite8(thr, priv->membase + PCH_UART_THR); in pch_uart_hal_write()
570 struct uart_port *port = &priv->port; in pch_uart_hal_read()
572 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
573 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
575 lsr = ioread8(priv->membase + UART_LSR)) { in pch_uart_hal_read()
576 rbr = ioread8(priv->membase + PCH_UART_RBR); in pch_uart_hal_read()
579 port->icount.brk++; in pch_uart_hal_read()
593 return ioread8(priv->membase + UART_IIR) &\ in pch_uart_hal_get_iid()
599 return ioread8(priv->membase + UART_LSR); in pch_uart_hal_get_line_status()
606 lcr = ioread8(priv->membase + UART_LCR); in pch_uart_hal_set_break()
612 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_break()
618 struct uart_port *port = &priv->port; in push_rx()
619 struct tty_port *tport = &port->state->port; in push_rx()
630 struct uart_port *port = &priv->port; in pop_tx_x()
632 if (port->x_char) { in pop_tx_x()
633 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", in pop_tx_x()
634 __func__, port->x_char, jiffies); in pop_tx_x()
635 buf[0] = port->x_char; in pop_tx_x()
636 port->x_char = 0; in pop_tx_x()
646 struct uart_port *port = &priv->port; in dma_push_rx()
647 struct tty_port *tport = &port->state->port; in dma_push_rx()
652 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", in dma_push_rx()
653 size - room); in dma_push_rx()
657 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); in dma_push_rx()
659 port->icount.rx += room; in dma_push_rx()
669 if (priv->chan_tx) { in pch_free_dma()
670 dma_release_channel(priv->chan_tx); in pch_free_dma()
671 priv->chan_tx = NULL; in pch_free_dma()
673 if (priv->chan_rx) { in pch_free_dma()
674 dma_release_channel(priv->chan_rx); in pch_free_dma()
675 priv->chan_rx = NULL; in pch_free_dma()
678 if (priv->rx_buf_dma) { in pch_free_dma()
679 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, in pch_free_dma()
680 priv->rx_buf_dma); in pch_free_dma()
681 priv->rx_buf_virt = NULL; in pch_free_dma()
682 priv->rx_buf_dma = 0; in pch_free_dma()
692 if ((chan->chan_id == param->chan_id) && (param->dma_dev == in filter()
693 chan->device->dev)) { in filter()
694 chan->private = param; in filter()
713 dma_dev = pci_get_slot(priv->pdev->bus, in pch_request_dma()
714 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); in pch_request_dma()
717 param = &priv->param_tx; in pch_request_dma()
718 param->dma_dev = &dma_dev->dev; in pch_request_dma()
719 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ in pch_request_dma()
721 param->tx_reg = port->mapbase + UART_TX; in pch_request_dma()
724 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", in pch_request_dma()
728 priv->chan_tx = chan; in pch_request_dma()
731 param = &priv->param_rx; in pch_request_dma()
732 param->dma_dev = &dma_dev->dev; in pch_request_dma()
733 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ in pch_request_dma()
735 param->rx_reg = port->mapbase + UART_RX; in pch_request_dma()
738 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", in pch_request_dma()
740 dma_release_channel(priv->chan_tx); in pch_request_dma()
741 priv->chan_tx = NULL; in pch_request_dma()
746 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, in pch_request_dma()
747 &priv->rx_buf_dma, GFP_KERNEL); in pch_request_dma()
748 priv->chan_rx = chan; in pch_request_dma()
754 struct uart_port *port = &priv->port; in pch_dma_rx_complete()
757 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); in pch_dma_rx_complete()
758 count = dma_push_rx(priv, priv->trigger_level); in pch_dma_rx_complete()
760 tty_flip_buffer_push(&port->state->port); in pch_dma_rx_complete()
761 async_tx_ack(priv->desc_rx); in pch_dma_rx_complete()
769 struct uart_port *port = &priv->port; in pch_dma_tx_complete()
770 struct circ_buf *xmit = &port->state->xmit; in pch_dma_tx_complete()
771 struct scatterlist *sg = priv->sg_tx_p; in pch_dma_tx_complete()
774 for (i = 0; i < priv->nent; i++, sg++) { in pch_dma_tx_complete()
775 xmit->tail += sg_dma_len(sg); in pch_dma_tx_complete()
776 port->icount.tx += sg_dma_len(sg); in pch_dma_tx_complete()
778 xmit->tail &= UART_XMIT_SIZE - 1; in pch_dma_tx_complete()
779 async_tx_ack(priv->desc_tx); in pch_dma_tx_complete()
780 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE); in pch_dma_tx_complete()
781 priv->tx_dma_use = 0; in pch_dma_tx_complete()
782 priv->nent = 0; in pch_dma_tx_complete()
783 priv->orig_nent = 0; in pch_dma_tx_complete()
784 kfree(priv->sg_tx_p); in pch_dma_tx_complete()
791 struct uart_port *port = &priv->port; in pop_tx()
792 struct circ_buf *xmit = &port->state->xmit; in pop_tx()
799 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in pop_tx()
800 int sz = min(size - count, cnt_to_end); in pop_tx()
801 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); in pop_tx()
802 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); in pop_tx()
807 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", in pop_tx()
808 count, size - count, jiffies); in pop_tx()
818 if (!priv->start_rx) { in handle_rx_to()
823 buf = &priv->rxbuf; in handle_rx_to()
825 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); in handle_rx_to()
826 ret = push_rx(priv, buf->buf, rx_size); in handle_rx_to()
829 } while (rx_size == buf->size); in handle_rx_to()
841 struct uart_port *port = &priv->port; in dma_handle_rx()
846 sg = &priv->sg_rx; in dma_handle_rx()
848 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ in dma_handle_rx()
850 sg_dma_len(sg) = priv->trigger_level; in dma_handle_rx()
852 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), in dma_handle_rx()
853 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); in dma_handle_rx()
855 sg_dma_address(sg) = priv->rx_buf_dma; in dma_handle_rx()
857 desc = dmaengine_prep_slave_sg(priv->chan_rx, in dma_handle_rx()
864 priv->desc_rx = desc; in dma_handle_rx()
865 desc->callback = pch_dma_rx_complete; in dma_handle_rx()
866 desc->callback_param = priv; in dma_handle_rx()
867 desc->tx_submit(desc); in dma_handle_rx()
868 dma_async_issue_pending(priv->chan_rx); in dma_handle_rx()
875 struct uart_port *port = &priv->port; in handle_tx()
876 struct circ_buf *xmit = &port->state->xmit; in handle_tx()
882 if (!priv->start_tx) { in handle_tx()
883 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in handle_tx()
886 priv->tx_empty = 1; in handle_tx()
890 fifo_size = max(priv->fifo_size, 1); in handle_tx()
892 if (pop_tx_x(priv, xmit->buf)) { in handle_tx()
893 pch_uart_hal_write(priv, xmit->buf, 1); in handle_tx()
894 port->icount.tx++; in handle_tx()
896 fifo_size--; in handle_tx()
898 size = min(xmit->head - xmit->tail, fifo_size); in handle_tx()
904 port->icount.tx += tx_size; in handle_tx()
908 priv->tx_empty = tx_empty; in handle_tx()
920 struct uart_port *port = &priv->port; in dma_handle_tx()
921 struct circ_buf *xmit = &port->state->xmit; in dma_handle_tx()
932 if (!priv->start_tx) { in dma_handle_tx()
933 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in dma_handle_tx()
936 priv->tx_empty = 1; in dma_handle_tx()
940 if (priv->tx_dma_use) { in dma_handle_tx()
941 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", in dma_handle_tx()
944 priv->tx_empty = 1; in dma_handle_tx()
948 fifo_size = max(priv->fifo_size, 1); in dma_handle_tx()
949 if (pop_tx_x(priv, xmit->buf)) { in dma_handle_tx()
950 pch_uart_hal_write(priv, xmit->buf, 1); in dma_handle_tx()
951 port->icount.tx++; in dma_handle_tx()
952 fifo_size--; in dma_handle_tx()
955 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, in dma_handle_tx()
956 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, in dma_handle_tx()
957 xmit->tail, UART_XMIT_SIZE)); in dma_handle_tx()
959 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); in dma_handle_tx()
975 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", in dma_handle_tx()
978 priv->tx_dma_use = 1; in dma_handle_tx()
980 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); in dma_handle_tx()
981 if (!priv->sg_tx_p) { in dma_handle_tx()
982 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); in dma_handle_tx()
986 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ in dma_handle_tx()
987 sg = priv->sg_tx_p; in dma_handle_tx()
990 if (i == (num - 1)) in dma_handle_tx()
991 sg_set_page(sg, virt_to_page(xmit->buf), in dma_handle_tx()
994 sg_set_page(sg, virt_to_page(xmit->buf), in dma_handle_tx()
998 sg = priv->sg_tx_p; in dma_handle_tx()
999 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); in dma_handle_tx()
1001 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); in dma_handle_tx()
1004 priv->orig_nent = num; in dma_handle_tx()
1005 priv->nent = nent; in dma_handle_tx()
1008 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + in dma_handle_tx()
1011 ~(UART_XMIT_SIZE - 1)) + sg->offset; in dma_handle_tx()
1012 if (i == (nent - 1)) in dma_handle_tx()
1018 desc = dmaengine_prep_slave_sg(priv->chan_tx, in dma_handle_tx()
1019 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, in dma_handle_tx()
1022 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", in dma_handle_tx()
1026 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); in dma_handle_tx()
1027 priv->desc_tx = desc; in dma_handle_tx()
1028 desc->callback = pch_dma_tx_complete; in dma_handle_tx()
1029 desc->callback_param = priv; in dma_handle_tx()
1031 desc->tx_submit(desc); in dma_handle_tx()
1033 dma_async_issue_pending(priv->chan_tx); in dma_handle_tx()
1040 struct uart_port *port = &priv->port; in pch_uart_err_ir()
1041 struct tty_struct *tty = tty_port_tty_get(&port->state->port); in pch_uart_err_ir()
1049 port->icount.frame++; in pch_uart_err_ir()
1054 port->icount.parity++; in pch_uart_err_ir()
1059 port->icount.overrun++; in pch_uart_err_ir()
1065 dev_err(&priv->pdev->dev, error_msg[i]); in pch_uart_err_ir()
1082 spin_lock_irqsave(&priv->lock, flags); in pch_uart_interrupt()
1100 if (priv->use_dma) { in pch_uart_interrupt()
1119 if (priv->use_dma) in pch_uart_interrupt()
1133 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, in pch_uart_interrupt()
1135 ret = -1; in pch_uart_interrupt()
1142 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_interrupt()
1153 if (priv->tx_empty) in pch_uart_tx_empty()
1196 if (priv->mcr & UART_MCR_AFE) in pch_uart_set_mctrl()
1200 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl()
1207 priv->start_tx = 0; in pch_uart_stop_tx()
1208 priv->tx_dma_use = 0; in pch_uart_stop_tx()
1217 if (priv->use_dma) { in pch_uart_start_tx()
1218 if (priv->tx_dma_use) { in pch_uart_start_tx()
1219 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", in pch_uart_start_tx()
1225 priv->start_tx = 1; in pch_uart_start_tx()
1233 priv->start_rx = 0; in pch_uart_stop_rx()
1253 spin_lock_irqsave(&priv->lock, flags); in pch_uart_break_ctl()
1255 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_break_ctl()
1267 priv->tx_empty = 1; in pch_uart_startup()
1269 if (port->uartclk) in pch_uart_startup()
1270 priv->uartclk = port->uartclk; in pch_uart_startup()
1272 port->uartclk = priv->uartclk; in pch_uart_startup()
1281 switch (priv->fifo_size) { in pch_uart_startup()
1297 switch (priv->trigger) { in pch_uart_startup()
1302 trigger_level = priv->fifo_size / 4; in pch_uart_startup()
1305 trigger_level = priv->fifo_size / 2; in pch_uart_startup()
1309 trigger_level = priv->fifo_size - (priv->fifo_size / 8); in pch_uart_startup()
1313 priv->trigger_level = trigger_level; in pch_uart_startup()
1315 fifo_size, priv->trigger); in pch_uart_startup()
1319 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, in pch_uart_startup()
1320 priv->irq_name, priv); in pch_uart_startup()
1324 if (priv->use_dma) in pch_uart_startup()
1327 priv->start_rx = 1; in pch_uart_startup()
1346 dev_err(priv->port.dev, in pch_uart_shutdown()
1351 free_irq(priv->port.irq, priv); in pch_uart_shutdown()
1366 switch (termios->c_cflag & CSIZE) { in pch_uart_set_termios()
1380 if (termios->c_cflag & CSTOPB) in pch_uart_set_termios()
1385 if (termios->c_cflag & PARENB) { in pch_uart_set_termios()
1386 if (termios->c_cflag & PARODD) in pch_uart_set_termios()
1395 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) in pch_uart_set_termios()
1396 priv->mcr |= UART_MCR_AFE; in pch_uart_set_termios()
1398 priv->mcr &= ~UART_MCR_AFE; in pch_uart_set_termios()
1400 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ in pch_uart_set_termios()
1402 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); in pch_uart_set_termios()
1404 spin_lock_irqsave(&priv->lock, flags); in pch_uart_set_termios()
1405 spin_lock(&port->lock); in pch_uart_set_termios()
1407 uart_update_timeout(port, termios->c_cflag, baud); in pch_uart_set_termios()
1412 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); in pch_uart_set_termios()
1418 spin_unlock(&port->lock); in pch_uart_set_termios()
1419 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_set_termios()
1432 pci_iounmap(priv->pdev, priv->membase); in pch_uart_release_port()
1433 pci_release_regions(priv->pdev); in pch_uart_release_port()
1443 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); in pch_uart_request_port()
1445 return -EBUSY; in pch_uart_request_port()
1447 membase = pci_iomap(priv->pdev, 1, 0); in pch_uart_request_port()
1449 pci_release_regions(priv->pdev); in pch_uart_request_port()
1450 return -EBUSY; in pch_uart_request_port()
1452 priv->membase = port->membase = membase; in pch_uart_request_port()
1463 port->type = priv->port_type; in pch_uart_config_port()
1474 if (serinfo->flags & UPF_LOW_LATENCY) { in pch_uart_verify_port()
1475 dev_info(priv->port.dev, in pch_uart_verify_port()
1476 "PCH UART : Use PIO Mode (without DMA)\n"); in pch_uart_verify_port()
1477 priv->use_dma = 0; in pch_uart_verify_port()
1478 serinfo->flags &= ~UPF_LOW_LATENCY; in pch_uart_verify_port()
1481 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", in pch_uart_verify_port()
1483 return -EOPNOTSUPP; in pch_uart_verify_port()
1485 if (!priv->use_dma) { in pch_uart_verify_port()
1487 if (priv->chan_rx) in pch_uart_verify_port()
1488 priv->use_dma = 1; in pch_uart_verify_port()
1490 dev_info(priv->port.dev, "PCH UART: %s\n", in pch_uart_verify_port()
1491 priv->use_dma ? in pch_uart_verify_port()
1508 status = ioread8(up->membase + UART_LSR); in wait_for_xmitr()
1512 if (--tmout == 0) in wait_for_xmitr()
1518 if (up->port.flags & UPF_CONS_FLOW) { in wait_for_xmitr()
1520 for (tmout = 1000000; tmout; tmout--) { in wait_for_xmitr()
1521 unsigned int msr = ioread8(up->membase + UART_MSR); in wait_for_xmitr()
1533 * Console polling routines for communicate via uart while
1540 u8 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_get_poll_char()
1545 return ioread8(priv->membase + PCH_UART_RBR); in pch_uart_get_poll_char()
1559 ier = ioread8(priv->membase + UART_IER); in pch_uart_put_poll_char()
1566 iowrite8(c, priv->membase + PCH_UART_THR); in pch_uart_put_poll_char()
1573 iowrite8(ier, priv->membase + UART_IER); in pch_uart_put_poll_char()
1609 iowrite8(ch, priv->membase + PCH_UART_THR); in pch_console_putchar()
1627 priv = pch_uart_ports[co->index]; in pch_console_write()
1632 if (priv->port.sysrq) { in pch_console_write()
1638 priv_locked = spin_trylock(&priv->lock); in pch_console_write()
1639 port_locked = spin_trylock(&priv->port.lock); in pch_console_write()
1641 spin_lock(&priv->lock); in pch_console_write()
1642 spin_lock(&priv->port.lock); in pch_console_write()
1648 ier = ioread8(priv->membase + UART_IER); in pch_console_write()
1652 uart_console_write(&priv->port, s, count, pch_console_putchar); in pch_console_write()
1659 iowrite8(ier, priv->membase + UART_IER); in pch_console_write()
1662 spin_unlock(&priv->port.lock); in pch_console_write()
1664 spin_unlock(&priv->lock); in pch_console_write()
1677 * Check whether an invalid uart number has been specified, and in pch_console_setup()
1681 if (co->index >= PCH_UART_NR) in pch_console_setup()
1682 co->index = 0; in pch_console_setup()
1683 port = &pch_uart_ports[co->index]->port; in pch_console_setup()
1685 if (!port || (!port->iobase && !port->membase)) in pch_console_setup()
1686 return -ENODEV; in pch_console_setup()
1688 port->uartclk = pch_uart_get_uartclk(); in pch_console_setup()
1704 .index = -1,
1731 int fifosize; in pch_uart_init_port() local
1736 board = &drv_dat[id->driver_data]; in pch_uart_init_port()
1737 port_type = board->port_type; in pch_uart_init_port()
1749 fifosize = 256; /* EG20T/ML7213: UART0 */ in pch_uart_init_port()
1752 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ in pch_uart_init_port()
1755 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); in pch_uart_init_port()
1762 spin_lock_init(&priv->lock); in pch_uart_init_port()
1766 priv->mapbase = mapbase; in pch_uart_init_port()
1767 priv->iobase = iobase; in pch_uart_init_port()
1768 priv->pdev = pdev; in pch_uart_init_port()
1769 priv->tx_empty = 1; in pch_uart_init_port()
1770 priv->rxbuf.buf = rxbuf; in pch_uart_init_port()
1771 priv->rxbuf.size = PAGE_SIZE; in pch_uart_init_port()
1773 priv->fifo_size = fifosize; in pch_uart_init_port()
1774 priv->uartclk = pch_uart_get_uartclk(); in pch_uart_init_port()
1775 priv->port_type = port_type; in pch_uart_init_port()
1776 priv->port.dev = &pdev->dev; in pch_uart_init_port()
1777 priv->port.iobase = iobase; in pch_uart_init_port()
1778 priv->port.membase = NULL; in pch_uart_init_port()
1779 priv->port.mapbase = mapbase; in pch_uart_init_port()
1780 priv->port.irq = pdev->irq; in pch_uart_init_port()
1781 priv->port.iotype = UPIO_PORT; in pch_uart_init_port()
1782 priv->port.ops = &pch_uart_ops; in pch_uart_init_port()
1783 priv->port.flags = UPF_BOOT_AUTOCONF; in pch_uart_init_port()
1784 priv->port.fifosize = fifosize; in pch_uart_init_port()
1785 priv->port.line = board->line_no; in pch_uart_init_port()
1786 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); in pch_uart_init_port()
1787 priv->trigger = PCH_UART_HAL_TRIGGER_M; in pch_uart_init_port()
1789 snprintf(priv->irq_name, IRQ_NAME_SIZE, in pch_uart_init_port()
1791 priv->port.line); in pch_uart_init_port()
1793 spin_lock_init(&priv->port.lock); in pch_uart_init_port()
1796 priv->trigger_level = 1; in pch_uart_init_port()
1797 priv->fcr = 0; in pch_uart_init_port()
1799 if (pdev->dev.of_node) in pch_uart_init_port()
1800 of_property_read_u32(pdev->dev.of_node, "clock-frequency" in pch_uart_init_port()
1804 pch_uart_ports[board->line_no] = priv; in pch_uart_init_port()
1806 ret = uart_add_one_port(&pch_uart_driver, &priv->port); in pch_uart_init_port()
1810 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_init_port()
1818 pch_uart_ports[board->line_no] = NULL; in pch_uart_init_port()
1832 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_exit_port()
1834 uart_remove_one_port(&pch_uart_driver, &priv->port); in pch_uart_exit_port()
1835 free_page((unsigned long)priv->rxbuf.buf); in pch_uart_exit_port()
1845 pch_uart_ports[priv->port.line] = NULL; in pch_uart_pci_remove()
1857 uart_suspend_port(&pch_uart_driver, &priv->port); in pch_uart_pci_suspend()
1866 uart_resume_port(&pch_uart_driver, &priv->port); in pch_uart_pci_resume()
1909 ret = -EBUSY; in pch_uart_pci_probe()
1939 /* register as UART driver */ in pch_uart_module_init()
1961 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1969 "Override UART default or board specific UART clock");