163 	st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_empty()
185 	unsigned int ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
188 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
197 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_start_tx()
202 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
204 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
211 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
213 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
215 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
217 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
226 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
231 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
243 			ch = readl(port->membase + UART_RBR(port));  in mvebu_uart_rx_chars()
291 		status = readl(port->membase + UART_STAT);  in mvebu_uart_rx_chars()
304 		writel(port->x_char, port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
316 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
323 		st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_chars()
338 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_isr()
353 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_rx_isr()
365 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_isr()
380 	       port->membase + UART_CTRL(port));  in mvebu_uart_startup()
384 	ret = readl(port->membase + UART_STAT);  in mvebu_uart_startup()
386 	writel(ret, port->membase + UART_STAT);  in mvebu_uart_startup()
388 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));  in mvebu_uart_startup()
390 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_startup()
392 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_startup()
435 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_shutdown()
466 	brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
469 	writel(brdv, port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
471 	osamp = readl(port->membase + UART_OSAMP);  in mvebu_uart_baud_rate_set()
473 	writel(osamp, port->membase + UART_OSAMP);  in mvebu_uart_baud_rate_set()
552 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_get_poll_char()
557 	return readl(port->membase + UART_RBR(port));  in mvebu_uart_get_poll_char()
565 		st = readl(port->membase + UART_STAT);  in mvebu_uart_put_poll_char()
573 	writel(c, port->membase + UART_TSH(port));  in mvebu_uart_put_poll_char()
606 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
612 	writel(c, port->membase + UART_STD_TSH);  in mvebu_uart_putc()
615 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
634 	if (!device->port.membase)  in mvebu_uart_early_console_setup()
650 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,  in wait_for_xmitr()
658 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,  in wait_for_xmite()
665 	writel(ch, port->membase + UART_TSH(port));  in mvebu_uart_console_putchar()
681 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;  in mvebu_uart_console_write()
682 	intr = readl(port->membase + UART_INTR(port)) &  in mvebu_uart_console_write()
684 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
685 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
692 		writel(ier, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
695 		ctl = intr | readl(port->membase + UART_INTR(port));  in mvebu_uart_console_write()
696 		writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
716 	if (!port->mapbase || !port->membase) {  in mvebu_uart_console_setup()
768 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));  in mvebu_uart_suspend()
769 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));  in mvebu_uart_suspend()
770 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_suspend()
771 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));  in mvebu_uart_suspend()
772 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);  in mvebu_uart_suspend()
773 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_suspend()
774 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);  in mvebu_uart_suspend()
786 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));  in mvebu_uart_resume()
787 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));  in mvebu_uart_resume()
788 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));  in mvebu_uart_resume()
789 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));  in mvebu_uart_resume()
790 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);  in mvebu_uart_resume()
791 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);  in mvebu_uart_resume()
792 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);  in mvebu_uart_resume()
860 	port->membase = devm_ioremap_resource(&pdev->dev, reg);  in mvebu_uart_probe()
861 	if (IS_ERR(port->membase))  in mvebu_uart_probe()
862 		return PTR_ERR(port->membase);  in mvebu_uart_probe()
919 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));  in mvebu_uart_probe()
921 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_probe()