Lines Matching refs:UART_INTR
147 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) macro
185 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
188 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
202 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
204 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
215 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
217 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
390 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
392 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
435 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
682 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
685 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
695 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
696 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
771 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
789 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()