59 #define UART_CR				0x0010  macro
391 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
448 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
449 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
554 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
642 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
643 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
665 	msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);  in msm_start_rx_dma()
666 	msm_write(uart, UART_CR_RX_ENABLE, UART_CR);  in msm_start_rx_dma()
668 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
670 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
708 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
763 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
765 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
784 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
928 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
948 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
954 			msm_write(port, val, UART_CR);  in msm_uart_irq()
956 			msm_write(port, val, UART_CR);  in msm_uart_irq()
995 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
996 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
997 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
998 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
999 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
1000 	msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_reset()
1019 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
1029 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
1031 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
1151 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
1155 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
1164 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
1166 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
1453 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1457 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1460 				  UART_CR);  in msm_poll_get_char_dm()