Lines Matching +full:rs485 +full:- +full:rts +full:- +full:active +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0+
30 #include <linux/dma-mapping.h>
33 #include <linux/platform_data/dma-imx.h>
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127 #define USR1_RTSS (1<<14) /* RTS pin status */
129 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
160 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define DRIVER_NAME "IMX-uart"
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 sport->ucr1 = val; in imx_uart_writel()
283 sport->ucr2 = val; in imx_uart_writel()
286 sport->ucr3 = val; in imx_uart_writel()
289 sport->ucr4 = val; in imx_uart_writel()
292 sport->ufcr = val; in imx_uart_writel()
297 writel(val, sport->port.membase + offset); in imx_uart_writel()
304 return sport->ucr1; in imx_uart_readl()
313 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
314 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
315 return sport->ucr2; in imx_uart_readl()
318 return sport->ucr3; in imx_uart_readl()
321 return sport->ucr4; in imx_uart_readl()
324 return sport->ufcr; in imx_uart_readl()
327 return readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->devdata->uts_reg; in imx_uart_uts_reg()
338 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
343 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
348 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
353 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
363 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
364 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
365 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
372 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
373 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
374 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
383 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
384 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
393 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
394 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
413 if (sport->dma_is_enabled) { in imx_uart_start_rx()
431 if (sport->tx_state == OFF) in imx_uart_stop_tx()
438 if (sport->dma_is_txing) in imx_uart_stop_tx()
454 /* in rs485 mode disable transmitter */ in imx_uart_stop_tx()
455 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
456 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
457 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
458 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
459 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
463 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
464 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
467 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
470 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
478 sport->tx_state = OFF; in imx_uart_stop_tx()
481 sport->tx_state = OFF; in imx_uart_stop_tx()
494 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
511 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
513 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
521 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
523 if (sport->port.x_char) { in imx_uart_transmit_buffer()
525 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
526 sport->port.icount.tx++; in imx_uart_transmit_buffer()
527 sport->port.x_char = 0; in imx_uart_transmit_buffer()
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
532 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
536 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
539 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
544 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
557 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
560 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in imx_uart_transmit_buffer()
561 sport->port.icount.tx++; in imx_uart_transmit_buffer()
565 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
568 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
574 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
575 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
579 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
581 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
588 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
589 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
593 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
596 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
606 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
612 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
613 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
615 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
616 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
620 if (sport->dma_is_txing) in imx_uart_dma_tx()
627 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
629 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
630 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
633 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
635 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
636 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
653 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
654 desc->callback_param = sport; in imx_uart_dma_tx()
664 sport->dma_is_txing = 1; in imx_uart_dma_tx()
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
680 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
685 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
686 if (sport->tx_state == OFF) { in imx_uart_start_tx()
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
694 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in imx_uart_start_tx()
697 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
698 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
699 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
703 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
704 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
706 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
711 * tx-callback. in imx_uart_start_tx()
713 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
719 sport->tx_state = SEND; in imx_uart_start_tx()
722 sport->tx_state = SEND; in imx_uart_start_tx()
725 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
730 if (sport->dma_is_enabled) { in imx_uart_start_tx()
731 if (sport->port.x_char) { in imx_uart_start_tx()
732 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
733 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
741 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
755 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
756 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
766 spin_lock(&sport->port.lock); in imx_uart_rtsint()
770 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
779 spin_lock(&sport->port.lock); in imx_uart_txint()
781 spin_unlock(&sport->port.lock); in imx_uart_txint()
789 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
795 sport->port.icount.rx++; in __imx_uart_rxint()
802 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
806 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
811 sport->port.icount.brk++; in __imx_uart_rxint()
813 sport->port.icount.parity++; in __imx_uart_rxint()
815 sport->port.icount.frame++; in __imx_uart_rxint()
817 sport->port.icount.overrun++; in __imx_uart_rxint()
819 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
825 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
836 sport->port.sysrq = 0; in __imx_uart_rxint()
839 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
843 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
857 spin_lock(&sport->port.lock); in imx_uart_rxint()
861 spin_unlock(&sport->port.lock); in imx_uart_rxint()
869 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
884 if (sport->dte_mode) in imx_uart_get_hwmctrl()
899 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
904 sport->old_status = status; in imx_uart_mctrl_check()
907 sport->port.icount.rng++; in imx_uart_mctrl_check()
909 sport->port.icount.dsr++; in imx_uart_mctrl_check()
911 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
913 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
915 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
924 spin_lock(&sport->port.lock); in imx_uart_int()
989 sport->port.icount.overrun++; in imx_uart_int()
994 spin_unlock(&sport->port.lock); in imx_uart_int()
1010 if (sport->dma_is_txing) in imx_uart_tx_empty()
1022 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1033 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1037 * Turn off autoRTS if RTS is lowered and restore autoRTS in imx_uart_set_mctrl()
1038 * setting if RTS is raised. in imx_uart_set_mctrl()
1065 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1077 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1086 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1090 * This is our per-port timeout handler, for checking the
1098 if (sport->port.state) { in imx_uart_timeout()
1099 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1101 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1103 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1118 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1119 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1120 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1122 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1128 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1135 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1138 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1141 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1143 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1149 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1152 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1153 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1155 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1156 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1159 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1162 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1166 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1169 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1173 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1175 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1177 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1178 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1184 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1190 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1191 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1192 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1196 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1197 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1199 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1203 return -EINVAL; in imx_uart_start_rx_dma()
1207 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1213 return -EINVAL; in imx_uart_start_rx_dma()
1215 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1216 desc->callback_param = sport; in imx_uart_start_rx_dma()
1219 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1220 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1227 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1234 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1236 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1238 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1242 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1245 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1251 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1275 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1276 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1277 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1278 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1279 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1280 kfree(sport->rx_buf); in imx_uart_dma_exit()
1281 sport->rx_buf = NULL; in imx_uart_dma_exit()
1284 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1285 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1286 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1287 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1294 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1298 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1299 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1301 ret = -EINVAL; in imx_uart_dma_init()
1306 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1309 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1310 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1316 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1317 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1318 if (!sport->rx_buf) { in imx_uart_dma_init()
1319 ret = -ENOMEM; in imx_uart_dma_init()
1322 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1325 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1326 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1328 ret = -EINVAL; in imx_uart_dma_init()
1333 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1336 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1359 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1373 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1387 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1390 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1392 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1413 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1421 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1432 if (sport->have_rtscts) in imx_uart_startup()
1438 if (!sport->dma_is_enabled) in imx_uart_startup()
1440 if (sport->inverted_rx) in imx_uart_startup()
1448 if (sport->inverted_tx) in imx_uart_startup()
1454 if (sport->dte_mode) in imx_uart_startup()
1462 if (!sport->have_rtscts) in imx_uart_startup()
1465 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1475 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1490 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1501 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1502 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1503 if (sport->dma_is_txing) { in imx_uart_shutdown()
1504 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1505 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1506 sport->dma_is_txing = 0; in imx_uart_shutdown()
1508 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1509 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1510 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1512 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1515 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1519 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1523 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1525 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1529 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1534 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1540 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1550 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1552 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1553 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1560 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1564 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1567 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1568 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1569 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1572 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1577 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1585 * and UTS[6-3]". in imx_uart_flush_buffer()
1599 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1616 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1624 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1625 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1626 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1627 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1631 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1636 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1639 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1649 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1652 if (!sport->have_rtscts) in imx_uart_set_termios()
1653 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1655 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1657 * RTS is mandatory for rs485 operation, so keep in imx_uart_set_termios()
1661 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1666 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1668 * Only let receiver control RTS output if we were not requested in imx_uart_set_termios()
1669 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1675 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1677 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1679 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1681 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1685 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1686 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1687 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1688 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1689 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1694 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1695 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1696 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1697 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1698 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1703 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1704 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1707 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1708 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1711 * Update the per-port timeout. in imx_uart_set_termios()
1713 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1715 /* custom-baudrate handling */ in imx_uart_set_termios()
1716 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1718 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1720 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1726 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1729 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1735 num -= 1; in imx_uart_set_termios()
1736 denom -= 1; in imx_uart_set_termios()
1749 * RTS/CTS handshake and suddenly gets broken bytes. in imx_uart_set_termios()
1759 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1764 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1765 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1767 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1774 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1785 sport->port.type = PORT_IMX; in imx_uart_config_port()
1799 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1800 ret = -EINVAL; in imx_uart_verify_port()
1801 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1802 ret = -EINVAL; in imx_uart_verify_port()
1803 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1804 ret = -EINVAL; in imx_uart_verify_port()
1805 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1806 ret = -EINVAL; in imx_uart_verify_port()
1807 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1808 ret = -EINVAL; in imx_uart_verify_port()
1809 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1810 ret = -EINVAL; in imx_uart_verify_port()
1811 if (ser->hub6 != 0) in imx_uart_verify_port()
1812 ret = -EINVAL; in imx_uart_verify_port()
1825 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1828 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1830 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1834 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1862 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1903 /* RTS is required to control the transmitter */ in imx_uart_rs485_config()
1904 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1905 rs485conf->flags &= ~SER_RS485_ENABLED; in imx_uart_rs485_config()
1907 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1908 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1909 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1910 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1911 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1915 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1922 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1923 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1924 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1927 port->rs485 = *rs485conf; in imx_uart_rs485_config()
1974 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
1980 if (sport->port.sysrq) in imx_uart_console_write()
1983 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1985 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2002 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2013 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2053 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2055 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2074 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2094 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2095 co->index = 0; in imx_uart_console_setup()
2096 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2098 return -ENODEV; in imx_uart_console_setup()
2101 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2112 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2115 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2119 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2121 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2134 .index = -1,
2159 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2160 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2161 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2162 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2172 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2173 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2174 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2175 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2186 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2195 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2197 return -ENOMEM; in imx_uart_probe()
2199 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2203 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2206 sport->port.line = ret; in imx_uart_probe()
2208 if (of_get_property(np, "uart-has-rtscts", NULL) || in imx_uart_probe()
2209 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) in imx_uart_probe()
2210 sport->have_rtscts = 1; in imx_uart_probe()
2212 if (of_get_property(np, "fsl,dte-mode", NULL)) in imx_uart_probe()
2213 sport->dte_mode = 1; in imx_uart_probe()
2215 if (of_get_property(np, "rts-gpios", NULL)) in imx_uart_probe()
2216 sport->have_rtsgpio = 1; in imx_uart_probe()
2218 if (of_get_property(np, "fsl,inverted-tx", NULL)) in imx_uart_probe()
2219 sport->inverted_tx = 1; in imx_uart_probe()
2221 if (of_get_property(np, "fsl,inverted-rx", NULL)) in imx_uart_probe()
2222 sport->inverted_rx = 1; in imx_uart_probe()
2224 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2225 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2226 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2228 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2229 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2232 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2233 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2234 sport->port.line); in imx_uart_probe()
2235 return -EINVAL; in imx_uart_probe()
2239 base = devm_ioremap_resource(&pdev->dev, res); in imx_uart_probe()
2249 sport->port.dev = &pdev->dev; in imx_uart_probe()
2250 sport->port.mapbase = res->start; in imx_uart_probe()
2251 sport->port.membase = base; in imx_uart_probe()
2252 sport->port.type = PORT_IMX; in imx_uart_probe()
2253 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2254 sport->port.irq = rxirq; in imx_uart_probe()
2255 sport->port.fifosize = 32; in imx_uart_probe()
2256 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2257 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2258 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2259 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2260 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2262 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2263 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2264 return PTR_ERR(sport->gpios); in imx_uart_probe()
2266 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2267 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2268 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2269 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2273 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2274 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2275 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2276 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2280 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2283 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2285 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2290 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2291 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2292 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2293 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2294 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2296 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2298 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2302 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2303 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2304 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2307 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) in imx_uart_probe()
2308 * signal cannot be set low during transmission in case the in imx_uart_probe()
2311 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2312 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2313 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2314 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2315 dev_err(&pdev->dev, in imx_uart_probe()
2316 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2318 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2325 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2356 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2358 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2359 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2360 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2361 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2368 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2369 dev_name(&pdev->dev), sport); in imx_uart_probe()
2371 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2376 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2377 dev_name(&pdev->dev), sport); in imx_uart_probe()
2379 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2384 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2385 dev_name(&pdev->dev), sport); in imx_uart_probe()
2387 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2392 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2393 dev_name(&pdev->dev), sport); in imx_uart_probe()
2395 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2400 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2404 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2411 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2418 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2419 if (!sport->context_saved) { in imx_uart_restore_context()
2420 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2424 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2425 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2426 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2427 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2428 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2429 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2430 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2431 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2432 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2433 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2434 sport->context_saved = false; in imx_uart_restore_context()
2435 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2443 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2444 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2445 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2446 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2447 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2448 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2449 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2450 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2451 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2452 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2453 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2454 sport->context_saved = true; in imx_uart_save_context()
2455 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2471 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2487 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2501 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2515 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2516 disable_irq(sport->port.irq); in imx_uart_suspend()
2518 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2535 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2536 enable_irq(sport->port.irq); in imx_uart_resume()
2538 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2547 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2549 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2556 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2558 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2580 .name = "imx-uart",
2612 MODULE_ALIAS("platform:imx-uart");