Lines Matching +full:rs485 +full:- +full:rx +full:- +full:during +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
11 #include <linux/dma-mapping.h>
24 /* All registers are 8-bit width */
113 /* 32-bit global registers only for i.MX7ULP/i.MX8x
118 /* 32-bit register definition */
232 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
235 #define DRIVER_NAME "fsl-lpuart"
315 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
316 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
317 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
318 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
319 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
329 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
330 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
335 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
340 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
345 switch (port->iotype) { in lpuart32_read()
347 return readl(port->membase + off); in lpuart32_read()
349 return ioread32be(port->membase + off); in lpuart32_read()
358 switch (port->iotype) { in lpuart32_write()
360 writel(val, port->membase + off); in lpuart32_write()
363 iowrite32be(val, port->membase + off); in lpuart32_write()
373 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
377 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
379 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
383 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
384 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
393 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
395 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
403 struct uart_port *port = &sport->port; in lpuart_global_reset()
410 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
412 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
417 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
424 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
432 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
434 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
450 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
451 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
464 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
465 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
466 struct device *dev = sport->port.dev; in lpuart_dma_tx()
467 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
470 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
473 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
475 if (xmit->tail < xmit->head || xmit->head == 0) { in lpuart_dma_tx()
476 sport->dma_tx_nents = 1; in lpuart_dma_tx()
477 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
479 sport->dma_tx_nents = 2; in lpuart_dma_tx()
481 sg_set_buf(sgl, xmit->buf + xmit->tail, in lpuart_dma_tx()
482 UART_XMIT_SIZE - xmit->tail); in lpuart_dma_tx()
483 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in lpuart_dma_tx()
486 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
489 dev_err(dev, "DMA mapping error for TX.\n"); in lpuart_dma_tx()
493 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
496 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
497 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
499 dev_err(dev, "Cannot prepare TX slave DMA!\n"); in lpuart_dma_tx()
503 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
504 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
505 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
506 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
512 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); in lpuart_stopped_or_empty()
518 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
519 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
520 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
523 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
524 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
525 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
529 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
532 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); in lpuart_dma_tx_complete()
534 sport->port.icount.tx += sport->dma_tx_bytes; in lpuart_dma_tx_complete()
535 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
536 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
539 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
541 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
542 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
546 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
548 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
551 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
556 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
558 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
560 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
562 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
576 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
579 dev_err(sport->port.dev, in lpuart_dma_tx_request()
589 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
590 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
596 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
599 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
600 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
601 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
602 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
603 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
609 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
611 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
613 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
615 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
622 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
642 sport->port.fifosize = 0; in lpuart_poll_init()
644 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
645 /* Disable Rx & Tx */ in lpuart_poll_init()
646 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
648 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
649 /* Enable Rx and Tx FIFO */ in lpuart_poll_init()
651 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
653 /* flush Tx and Rx FIFO */ in lpuart_poll_init()
655 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
658 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
659 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
660 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
663 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
664 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
666 /* Enable Rx and Tx */ in lpuart_poll_init()
667 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
668 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
677 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
682 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
685 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
694 sport->port.fifosize = 0; in lpuart32_poll_init()
696 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
698 /* Disable Rx & Tx */ in lpuart32_poll_init()
699 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
701 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
703 /* Enable Rx and Tx FIFO */ in lpuart32_poll_init()
704 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
706 /* flush Tx and Rx FIFO */ in lpuart32_poll_init()
707 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
710 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
711 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
712 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
715 /* Enable Rx and Tx */ in lpuart32_poll_init()
716 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
717 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
739 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_transmit_buffer()
741 if (sport->port.x_char) { in lpuart_transmit_buffer()
742 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_transmit_buffer()
743 sport->port.icount.tx++; in lpuart_transmit_buffer()
744 sport->port.x_char = 0; in lpuart_transmit_buffer()
748 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart_transmit_buffer()
749 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
754 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
755 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
756 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart_transmit_buffer()
757 sport->port.icount.tx++; in lpuart_transmit_buffer()
761 uart_write_wakeup(&sport->port); in lpuart_transmit_buffer()
764 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
769 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
772 if (sport->port.x_char) { in lpuart32_transmit_buffer()
773 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
774 sport->port.icount.tx++; in lpuart32_transmit_buffer()
775 sport->port.x_char = 0; in lpuart32_transmit_buffer()
779 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
780 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
784 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
787 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
788 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
789 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart32_transmit_buffer()
790 sport->port.icount.tx++; in lpuart32_transmit_buffer()
791 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
797 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
800 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
809 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
810 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
812 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
816 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
826 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
843 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
844 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
846 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
862 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
873 spin_lock(&sport->port.lock); in lpuart_txint()
875 spin_unlock(&sport->port.lock); in lpuart_txint()
881 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
882 unsigned char rx, sr; in lpuart_rxint() local
884 spin_lock(&sport->port.lock); in lpuart_rxint()
886 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
888 sport->port.icount.rx++; in lpuart_rxint()
893 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
894 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
896 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
901 sport->port.icount.parity++; in lpuart_rxint()
903 sport->port.icount.frame++; in lpuart_rxint()
908 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
914 sr &= sport->port.read_status_mask; in lpuart_rxint()
924 sport->port.sysrq = 0; in lpuart_rxint()
927 tty_insert_flip_char(port, rx, flg); in lpuart_rxint()
932 sport->port.icount.overrun += overrun; in lpuart_rxint()
938 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
939 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
942 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
949 spin_lock(&sport->port.lock); in lpuart32_txint()
951 spin_unlock(&sport->port.lock); in lpuart32_txint()
957 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
958 unsigned long rx, sr; in lpuart32_rxint() local
961 spin_lock(&sport->port.lock); in lpuart32_rxint()
963 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
965 sport->port.icount.rx++; in lpuart32_rxint()
970 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
971 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
972 rx &= UARTDATA_MASK; in lpuart32_rxint()
978 is_break = (sr & UARTSTAT_FE) && !rx; in lpuart32_rxint()
980 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
983 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
989 sport->port.icount.brk++; in lpuart32_rxint()
991 sport->port.icount.parity++; in lpuart32_rxint()
993 sport->port.icount.frame++; in lpuart32_rxint()
997 sport->port.icount.overrun++; in lpuart32_rxint()
999 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1005 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1020 tty_insert_flip_char(port, rx, flg); in lpuart32_rxint()
1024 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1034 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1037 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1038 readb(sport->port.membase + UARTDR); in lpuart_int()
1039 uart_handle_break(&sport->port); in lpuart_int()
1041 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1045 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1048 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1059 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1060 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1063 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1066 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1069 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1077 while (count--) { in lpuart_handle_sysrq_chars()
1086 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1089 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1090 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1091 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1092 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1093 ring->tail = 0; in lpuart_handle_sysrq()
1096 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1097 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1098 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1099 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1100 ring->tail = ring->head; in lpuart_handle_sysrq()
1106 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1109 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1110 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1115 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1119 lpuart32_read(&sport->port, UARTDATA); in lpuart_copy_rx_to_tty()
1122 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1124 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1127 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1132 /* Disable receiver during this operation... */ in lpuart_copy_rx_to_tty()
1133 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1135 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1138 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1141 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1143 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1153 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1156 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1158 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1162 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1166 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1168 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1170 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1172 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1173 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1177 /* CPU claims ownership of RX DMA buffer */ in lpuart_copy_rx_to_tty()
1178 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1182 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1183 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1188 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1189 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1194 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1200 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1202 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1204 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1205 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1211 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1212 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1214 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1215 ring->tail = 0; in lpuart_copy_rx_to_tty()
1216 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1220 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1221 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1222 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1223 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1224 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1225 ring->head = 0; in lpuart_copy_rx_to_tty()
1226 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1227 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1231 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1234 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1237 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1257 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1260 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1261 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1262 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1263 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1267 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; in lpuart_start_rx_dma()
1268 if (termios->c_cflag & PARENB) in lpuart_start_rx_dma()
1275 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1276 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); in lpuart_start_rx_dma()
1277 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1278 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1280 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1281 if (!ring->buf) in lpuart_start_rx_dma()
1282 return -ENOMEM; in lpuart_start_rx_dma()
1284 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1285 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1289 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1290 return -EINVAL; in lpuart_start_rx_dma()
1300 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1301 "DMA Rx slave config failed, err = %d\n", ret); in lpuart_start_rx_dma()
1305 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1306 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1307 sport->rx_sgl.length, in lpuart_start_rx_dma()
1308 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1311 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1312 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1313 return -EFAULT; in lpuart_start_rx_dma()
1316 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1317 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1318 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1322 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1324 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1326 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1327 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1337 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1340 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1341 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1342 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1343 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1344 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1345 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1349 struct serial_rs485 *rs485) in lpuart_config_rs485() argument
1354 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1356 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1359 rs485->delay_rts_before_send = 0; in lpuart_config_rs485()
1360 rs485->delay_rts_after_send = 0; in lpuart_config_rs485()
1361 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart_config_rs485()
1363 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1364 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1368 * RTS needs to be logic HIGH either during transfer _or_ after in lpuart_config_rs485()
1372 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart_config_rs485()
1374 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart_config_rs485()
1376 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart_config_rs485()
1377 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1378 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart_config_rs485()
1386 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1388 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1393 sport->port.rs485 = *rs485; in lpuart_config_rs485()
1395 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1400 struct serial_rs485 *rs485) in lpuart32_config_rs485() argument
1405 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1407 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1410 rs485->delay_rts_before_send = 0; in lpuart32_config_rs485()
1411 rs485->delay_rts_after_send = 0; in lpuart32_config_rs485()
1412 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart32_config_rs485()
1414 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1415 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1419 * RTS needs to be logic HIGH either during transfer _or_ after in lpuart32_config_rs485()
1423 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart32_config_rs485()
1425 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart32_config_rs485()
1427 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart32_config_rs485()
1428 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1429 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart32_config_rs485()
1437 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1439 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1444 sport->port.rs485 = *rs485; in lpuart32_config_rs485()
1446 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1455 reg = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1478 reg = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1485 writeb(reg, port->membase + UARTCR1); in lpuart_set_mctrl()
1506 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1511 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1531 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1535 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1537 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1539 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1541 /* flush Tx and Rx FIFO */ in lpuart_setup_watermark()
1543 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1546 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1547 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1548 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1551 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1552 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1555 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1564 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1566 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1574 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1578 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1581 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1584 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1588 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1591 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1600 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1602 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1607 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1608 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1609 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1614 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1615 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1616 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1617 "DMA tx channel request failed, operating without tx DMA (%ld)\n", in lpuart_request_dma()
1618 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1619 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1622 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1623 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1624 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1625 "DMA rx channel request failed, operating without rx DMA (%ld)\n", in lpuart_request_dma()
1626 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1627 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1636 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1639 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1642 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1646 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1647 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1649 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1650 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1653 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1654 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1660 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1668 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1671 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1678 /* set Rx DMA timeout */ in lpuart_rx_dma_startup()
1679 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1680 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1681 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1683 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1686 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1687 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1689 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1695 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1705 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1707 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1709 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1711 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1716 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_startup()
1723 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_startup()
1732 if (sport->lpuart_dma_rx_use) { in lpuart32_configure()
1734 temp = lpuart32_read(&sport->port, UARTWATER); in lpuart32_configure()
1736 lpuart32_write(&sport->port, temp, UARTWATER); in lpuart32_configure()
1738 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1739 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1741 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1743 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1753 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1755 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1757 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1759 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1764 * Although they support the RX/TXSIZE fields, their encoding is in lpuart32_startup()
1768 sport->rxfifo_size = 16; in lpuart32_startup()
1769 sport->txfifo_size = 16; in lpuart32_startup()
1770 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1775 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_startup()
1784 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_startup()
1790 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1791 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_shutdown()
1792 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1795 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1796 if (wait_event_interruptible(sport->dma_wait, in lpuart_dma_shutdown()
1797 !sport->dma_tx_in_progress) != false) { in lpuart_dma_shutdown()
1798 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1799 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_dma_shutdown()
1803 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1804 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1805 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1806 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1815 spin_lock_irqsave(&port->lock, flags); in lpuart_shutdown()
1817 /* disable Rx/Tx and interrupts */ in lpuart_shutdown()
1818 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1821 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1823 spin_unlock_irqrestore(&port->lock, flags); in lpuart_shutdown()
1835 spin_lock_irqsave(&port->lock, flags); in lpuart32_shutdown()
1837 /* disable Rx/Tx and interrupts */ in lpuart32_shutdown()
1843 spin_unlock_irqrestore(&port->lock, flags); in lpuart32_shutdown()
1856 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1859 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1860 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1861 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1862 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1863 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1864 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1868 * - (7,e/o,1) in lpuart_set_termios()
1869 * - (8,n,1) in lpuart_set_termios()
1870 * - (8,m/s,1) in lpuart_set_termios()
1871 * - (8,e/o,1) in lpuart_set_termios()
1873 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1874 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
1875 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1876 termios->c_cflag |= old_csize; in lpuart_set_termios()
1880 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
1881 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1884 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1885 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
1886 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1887 termios->c_cflag |= CS8; in lpuart_set_termios()
1893 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
1896 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
1897 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
1899 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
1904 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
1906 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
1907 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1908 termios->c_cflag |= PARENB; in lpuart_set_termios()
1910 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
1911 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1913 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1919 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
1921 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1931 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
1935 * baud rate and restart Rx DMA path. in lpuart_set_termios()
1937 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
1940 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1941 del_timer_sync(&sport->lpuart_timer); in lpuart_set_termios()
1942 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
1945 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
1947 sport->port.read_status_mask = 0; in lpuart_set_termios()
1948 if (termios->c_iflag & INPCK) in lpuart_set_termios()
1949 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
1950 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
1951 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1954 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
1955 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1956 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
1957 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
1958 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1963 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1964 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
1967 /* update the per-port timeout */ in lpuart_set_termios()
1968 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
1971 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
1975 sport->port.membase + UARTCR2); in lpuart_set_termios()
1977 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
1978 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
1983 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1984 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1985 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1986 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
1987 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1988 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1991 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1993 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1997 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2000 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
2008 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
2011 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
2012 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
2033 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2037 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2038 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2057 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2066 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2082 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2083 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2084 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2096 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2098 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2099 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2100 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2104 * - (7,e/o,1) in lpuart32_set_termios()
2105 * - (8,n,1) in lpuart32_set_termios()
2106 * - (8,m/s,1) in lpuart32_set_termios()
2107 * - (8,e/o,1) in lpuart32_set_termios()
2109 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2110 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2111 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2112 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2116 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2117 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2120 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2121 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2122 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2123 termios->c_cflag |= CS8; in lpuart32_set_termios()
2129 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2132 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2133 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2135 if (termios->c_cflag & CRTSCTS) { in lpuart32_set_termios()
2138 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2142 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2147 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2148 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2149 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2151 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2152 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2157 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2159 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2169 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2173 * baud rate and restart Rx DMA path. in lpuart32_set_termios()
2175 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2178 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2179 del_timer_sync(&sport->lpuart_timer); in lpuart32_set_termios()
2180 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2183 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2185 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2186 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2187 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2188 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2189 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2192 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2193 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2194 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2195 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2196 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2201 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2202 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2205 /* update the per-port timeout */ in lpuart32_set_termios()
2206 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2209 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2212 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2215 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2217 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2218 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2221 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2225 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2228 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2250 port->type = PORT_LPUART; in lpuart_config_port()
2257 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2258 ret = -EINVAL; in lpuart_verify_port()
2259 if (port->irq != ser->irq) in lpuart_verify_port()
2260 ret = -EINVAL; in lpuart_verify_port()
2261 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2262 ret = -EINVAL; in lpuart_verify_port()
2263 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2264 ret = -EINVAL; in lpuart_verify_port()
2265 if (port->iobase != ser->port) in lpuart_verify_port()
2266 ret = -EINVAL; in lpuart_verify_port()
2267 if (ser->hub6 != 0) in lpuart_verify_port()
2268 ret = -EINVAL; in lpuart_verify_port()
2326 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2338 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2344 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2346 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2349 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2352 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2354 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2357 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2359 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2362 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2368 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2374 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2376 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2379 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2382 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2384 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2387 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2389 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2392 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2406 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2413 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2428 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2430 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2434 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2444 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2455 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2462 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2477 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2490 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2507 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2508 co->index = 0; in lpuart_console_setup()
2510 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2512 return -ENODEV; in lpuart_console_setup()
2527 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2537 .index = -1,
2547 .index = -1,
2553 struct earlycon_device *dev = con->data; in lpuart_early_write()
2555 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2560 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2562 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2568 if (!device->port.membase) in lpuart_early_console_setup()
2569 return -ENODEV; in lpuart_early_console_setup()
2571 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2578 if (!device->port.membase) in lpuart32_early_console_setup()
2579 return -ENODEV; in lpuart32_early_console_setup()
2581 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2582 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2584 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2593 if (!device->port.membase) in ls1028a_early_console_setup()
2594 return -ENODEV; in ls1028a_early_console_setup()
2596 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2597 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2600 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2601 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2605 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2607 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2615 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2616 return -ENODEV; in lpuart32_imx_early_console_setup()
2618 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2619 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2620 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2624 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2625 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2626 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2627 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2648 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); in lpuart_probe()
2649 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2654 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2656 return -ENOMEM; in lpuart_probe()
2659 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
2660 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2661 return PTR_ERR(sport->port.membase); in lpuart_probe()
2663 sport->port.membase += sdata->reg_off; in lpuart_probe()
2664 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2665 sport->port.dev = &pdev->dev; in lpuart_probe()
2666 sport->port.type = PORT_LPUART; in lpuart_probe()
2667 sport->devtype = sdata->devtype; in lpuart_probe()
2671 sport->port.irq = ret; in lpuart_probe()
2672 sport->port.iotype = sdata->iotype; in lpuart_probe()
2674 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2676 sport->port.ops = &lpuart_pops; in lpuart_probe()
2677 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2678 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2681 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2683 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2685 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2686 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2687 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2688 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); in lpuart_probe()
2692 sport->baud_clk = NULL; in lpuart_probe()
2694 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2695 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2696 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2697 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); in lpuart_probe()
2706 dev_err(&pdev->dev, "port line is full, add device failed\n"); in lpuart_probe()
2709 sport->id_allocated = true; in lpuart_probe()
2712 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2713 ret = -EINVAL; in lpuart_probe()
2716 sport->port.line = ret; in lpuart_probe()
2721 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2723 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2725 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2729 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, in lpuart_probe()
2733 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, in lpuart_probe()
2740 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2748 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2752 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) in lpuart_probe()
2753 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); in lpuart_probe()
2755 if (sport->port.rs485.delay_rts_before_send || in lpuart_probe()
2756 sport->port.rs485.delay_rts_after_send) in lpuart_probe()
2757 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); in lpuart_probe()
2759 sport->port.rs485_config(&sport->port, &sport->port.rs485); in lpuart_probe()
2765 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2771 if (sport->id_allocated) in lpuart_probe()
2772 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); in lpuart_probe()
2780 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2782 if (sport->id_allocated) in lpuart_remove()
2783 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); in lpuart_remove()
2787 if (sport->dma_tx_chan) in lpuart_remove()
2788 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2790 if (sport->dma_rx_chan) in lpuart_remove()
2791 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2803 /* disable Rx/Tx and interrupts */ in lpuart_suspend()
2804 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
2806 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
2808 /* disable Rx/Tx and interrupts */ in lpuart_suspend()
2809 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
2811 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
2814 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
2817 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend()
2819 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
2821 * EDMA driver during suspend will forcefully release any in lpuart_suspend()
2822 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
2823 * is console port or 'no_console_suspend' is set the Rx DMA in lpuart_suspend()
2825 * Rx DMA path before suspend and start Rx DMA path on resume. in lpuart_suspend()
2828 del_timer_sync(&sport->lpuart_timer); in lpuart_suspend()
2829 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
2832 /* Disable Rx DMA to use UART port as wakeup source */ in lpuart_suspend()
2834 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
2835 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
2838 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
2839 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
2843 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
2844 sport->dma_tx_in_progress = false; in lpuart_suspend()
2845 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_suspend()
2848 if (sport->port.suspended && !irq_wake) in lpuart_suspend()
2857 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_resume()
2859 if (sport->port.suspended && !irq_wake) in lpuart_resume()
2867 if (sport->lpuart_dma_rx_use) { in lpuart_resume()
2872 sport->lpuart_dma_rx_use = false; in lpuart_resume()
2881 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
2892 .name = "fsl-lpuart",