288 static unsigned int pl011_read(const struct uart_amba_port *uap,  in pl011_read()  function
320 		status = pl011_read(uap, REG_FR);  in pl011_fifo_to_tty()
325 		ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;  in pl011_fifo_to_tty()
784 	if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {  in pl011_dma_tx_start()
1193 	while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)  in pl011_dma_shutdown()
1310 	cr = pl011_read(uap, REG_CR);  in pl011_rs485_tx_stop()
1417 	    pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_tx_char()
1432 	cr = pl011_read(uap, REG_CR);  in pl011_rs485_tx_start()
1501 	status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;  in pl011_modem_status()
1535 	pl011_read(uap, REG_ICR);  in check_apply_cts_event_workaround()
1536 	pl011_read(uap, REG_ICR);  in check_apply_cts_event_workaround()
1547 	status = pl011_read(uap, REG_RIS) & uap->im;  in pl011_int()
1571 			status = pl011_read(uap, REG_RIS) & uap->im;  in pl011_int()
1587 	unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;  in pl011_tx_empty()
1598 	unsigned int status = pl011_read(uap, REG_FR);  in pl011_get_mctrl()
1621 	cr = pl011_read(uap, REG_CR);  in pl011_set_mctrl()
1652 	lcr_h = pl011_read(uap, REG_LCRH_TX);  in pl011_break_ctl()
1668 	pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);  in pl011_quiesce_irqs()
1682 	pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,  in pl011_quiesce_irqs()
1698 	status = pl011_read(uap, REG_FR);  in pl011_get_poll_char()
1702 	return pl011_read(uap, REG_DR);  in pl011_get_poll_char()
1711 	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_put_poll_char()
1746 	uap->im = pl011_read(uap, REG_IMSC);  in pl011_hwinit()
1808 		if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)  in pl011_enable_interrupts()
1811 		pl011_read(uap, REG_DR);  in pl011_enable_interrupts()
1860 	uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;  in pl011_startup()
1901       val = pl011_read(uap, lcrh);  in pl011_shutdown_channel()
1917 	cr = pl011_read(uap, REG_CR);  in pl011_disable_uart()
2109 	old_cr = pl011_read(uap, REG_CR);  in pl011_set_termios()
2254 		u32 cr = pl011_read(uap, REG_CR);  in pl011_rs485_config()
2329 	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_console_putchar()
2356 		old_cr = pl011_read(uap, REG_CR);  in pl011_console_write()
2369 	while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)  in pl011_console_write()
2385 	if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {  in pl011_console_get_options()
2388 		lcr_h = pl011_read(uap, REG_LCRH_TX);  in pl011_console_get_options()
2403 		ibrd = pl011_read(uap, REG_IBRD);  in pl011_console_get_options()
2404 		fbrd = pl011_read(uap, REG_FBRD);  in pl011_console_get_options()
2409 			if (pl011_read(uap, REG_CR)  in pl011_console_get_options()