Lines Matching +full:0 +full:xa010
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
63 0xA000, 0x1000) },
65 0xA000, 0x1000) },
67 0xA000, 0x1000) },
81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" in moan_device()
98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) in setup_port()
102 port->port.iobase = 0; in setup_port()
109 port->port.mapbase = 0; in setup_port()
111 port->port.regshift = 0; in setup_port()
113 return 0; in setup_port()
123 unsigned int bar = 0, offset = board->first_offset; in addidata_apci7800_setup()
172 int rc = 0; in pci_hp_diva_init()
214 if (idx > 0) in pci_hp_diva_setup()
221 offset = 0x18; in pci_hp_diva_setup()
235 if (!(dev->subsystem_device & 0x1000)) in pci_inteli960ni_init()
239 pci_read_config_dword(dev, 0x44, &oldval); in pci_inteli960ni_init()
240 if (oldval == 0x00001000L) { /* RESET value */ in pci_inteli960ni_init()
244 return 0; in pci_inteli960ni_init()
258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { in pci_plx9050_init()
259 moan_device("no memory in bar 0", dev); in pci_plx9050_init()
260 return 0; in pci_plx9050_init()
263 irq_config = 0x41; in pci_plx9050_init()
266 irq_config = 0x43; in pci_plx9050_init()
278 irq_config = 0x5b; in pci_plx9050_init()
282 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_init()
285 writel(irq_config, p + 0x4c); in pci_plx9050_init()
290 readl(p + 0x4c); in pci_plx9050_init()
293 return 0; in pci_plx9050_init()
300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) in pci_plx9050_exit()
306 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_exit()
308 writel(0, p + 0x4c); in pci_plx9050_exit()
313 readl(p + 0x4c); in pci_plx9050_exit()
318 #define NI8420_INT_ENABLE_REG 0x38
319 #define NI8420_INT_ENABLE_BIT 0x2000
324 unsigned int bar = 0; in pci_ni8420_exit()
326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_exit()
343 #define MITE_IOWBSR1 0xc4
344 #define MITE_IOWCR1 0xf4
345 #define MITE_LCIMR1 0x08
346 #define MITE_LCIMR2 0x10
353 unsigned int bar = 0; in pci_ni8430_exit()
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_exit()
376 bar = 0; in sbs_setup()
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ in sbs_setup()
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ in sbs_setup()
383 offset += idx * board->uart_offset + 0xC00; in sbs_setup()
398 #define OCT_REG_CR_OFF 0x500
404 p = pci_ioremap_bar(dev, 0); in sbs_init()
409 writeb(0x10, p + OCT_REG_CR_OFF); in sbs_init()
411 writeb(0x0, p + OCT_REG_CR_OFF); in sbs_init()
414 writeb(0x4, p + OCT_REG_CR_OFF); in sbs_init()
417 return 0; in sbs_init()
428 p = pci_ioremap_bar(dev, 0); in sbs_exit()
431 writeb(0, p + OCT_REG_CR_OFF); in sbs_exit()
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
470 switch (dev->device & 0xfff8) { in pci_siig10x_init()
472 data = 0xffdf; in pci_siig10x_init()
475 data = 0xf7ff; in pci_siig10x_init()
478 data = 0xfffb; in pci_siig10x_init()
482 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_siig10x_init()
486 writew(readw(p + 0x28) & data, p + 0x28); in pci_siig10x_init()
487 readw(p + 0x28); in pci_siig10x_init()
489 return 0; in pci_siig10x_init()
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
500 pci_read_config_byte(dev, 0x6f, &data); in pci_siig20x_init()
501 pci_write_config_byte(dev, 0x6f, data & 0xef); in pci_siig20x_init()
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || in pci_siig20x_init()
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { in pci_siig20x_init()
506 pci_read_config_byte(dev, 0x73, &data); in pci_siig20x_init()
507 pci_write_config_byte(dev, 0x73, data & 0xef); in pci_siig20x_init()
509 return 0; in pci_siig20x_init()
514 unsigned int type = dev->device & 0xff00; in pci_siig_init()
516 if (type == 0x1000) in pci_siig_init()
518 else if (type == 0x2000) in pci_siig_init()
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; in pci_siig_setup()
536 return setup_port(priv, port, bar, offset, 0); in pci_siig_setup()
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) in pci_timedia_probe()
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { in pci_timedia_probe()
597 return 0; in pci_timedia_probe()
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { in pci_timedia_init()
607 for (j = 0; ids[j]; j++) in pci_timedia_init()
611 return 0; in pci_timedia_init()
623 unsigned int bar = 0, offset = board->first_offset; in pci_timedia_setup()
626 case 0: in pci_timedia_setup()
627 bar = 0; in pci_timedia_setup()
631 bar = 0; in pci_timedia_setup()
660 case 0: in titan_400l_800l_setup()
677 return 0; in pci_xircom_init()
683 unsigned int bar = 0; in pci_ni8420_init()
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_init()
687 return 0; in pci_ni8420_init()
699 return 0; in pci_ni8420_init()
702 #define MITE_IOWBSR1_WSIZE 0xa
703 #define MITE_IOWBSR1_WIN_OFFSET 0x800
707 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
714 unsigned int bar = 0; in pci_ni8430_init()
716 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_init()
718 return 0; in pci_ni8430_init()
731 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) in pci_ni8430_init()
739 /* Enable IO Bus Interrupt 0 */ in pci_ni8430_init()
746 return 0; in pci_ni8430_init()
750 #define NI8430_PORTCON 0x0f
788 (priv->dev->subsystem_device & 0xff00) == 0x3000) { in pci_netmos_9900_setup()
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) in pci_netmos_9900_setup()
794 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
814 pi = c & 0xff; in pci_netmos_9900_numports()
819 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { in pci_netmos_9900_numports()
820 /* two possibilities: 0x30ps encodes number of parallel and in pci_netmos_9900_numports()
821 * serial ports, or 0x1000 indicates *something*. This is not in pci_netmos_9900_numports()
823 * to offer all functionality on functions 0..2, while still in pci_netmos_9900_numports()
826 sub_serports = dev->subsystem_device & 0xf; in pci_netmos_9900_numports()
827 if (sub_serports > 0) in pci_netmos_9900_numports()
832 return 0; in pci_netmos_9900_numports()
836 return 0; in pci_netmos_9900_numports()
841 /* subdevice 0x00PS means <P> parallel, <S> serial */ in pci_netmos_init()
842 unsigned int num_serial = dev->subsystem_device & 0xf; in pci_netmos_init()
846 return 0; in pci_netmos_init()
849 dev->subsystem_device == 0x0299) in pci_netmos_init()
850 return 0; in pci_netmos_init()
864 if (num_serial == 0) { in pci_netmos_init()
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, in pci_ite887x_init()
904 0x200, 0x280, 0 }; in pci_ite887x_init()
910 i = 0; in pci_ite887x_init()
923 if (ret != 0xff) { in pci_ite887x_init()
939 type = inb(iobase->start + 0x18) & 0x0f; in pci_ite887x_init()
942 case 0x2: /* ITE8871 (1P) */ in pci_ite887x_init()
943 case 0xa: /* ITE8875 (1P) */ in pci_ite887x_init()
944 ret = 0; in pci_ite887x_init()
946 case 0xe: /* ITE8872 (2S1P) */ in pci_ite887x_init()
949 case 0x6: /* ITE8873 (1S) */ in pci_ite887x_init()
952 case 0x8: /* ITE8874 (2S) */ in pci_ite887x_init()
961 for (i = 0; i < ret; i++) { in pci_ite887x_init()
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), in pci_ite887x_init()
965 ioport &= 0x0000FF00; /* the actual base address */ in pci_ite887x_init()
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), in pci_ite887x_init()
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ in pci_ite887x_init()
978 /* disable interrupts (UARTx_Routing[3:0]) */ in pci_ite887x_init()
979 miscr &= ~(0xf << (12 - 4 * i)); in pci_ite887x_init()
986 if (ret <= 0) { in pci_ite887x_init()
997 /* the ioport is bit 0-15 in POSIO0R */ in pci_ite887x_exit()
999 ioport &= 0xffff; in pci_ite887x_exit()
1007 #define PCI_VENDOR_ID_ENDRUN 0x7401
1008 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1014 unsigned int number_uarts = 0; in pci_endrun_init()
1016 /* EndRun device is all 0xexxx */ in pci_endrun_init()
1018 (dev->device & 0xf000) != 0xe000) in pci_endrun_init()
1019 return 0; in pci_endrun_init()
1021 p = pci_iomap(dev, 0, 5); in pci_endrun_init()
1027 if (deviceID == 0x07000200) { in pci_endrun_init()
1046 unsigned int number_uarts = 0; in pci_oxsemi_tornado_init()
1048 /* OxSemi Tornado devices are all 0xCxxx */ in pci_oxsemi_tornado_init()
1050 (dev->device & 0xF000) != 0xC000) in pci_oxsemi_tornado_init()
1051 return 0; in pci_oxsemi_tornado_init()
1053 p = pci_iomap(dev, 0, 5); in pci_oxsemi_tornado_init()
1059 if (deviceID == 0x07000200) { in pci_oxsemi_tornado_init()
1084 #define QPCR_TEST_FOR1 0x3F
1085 #define QPCR_TEST_GET1 0x00
1086 #define QPCR_TEST_FOR2 0x40
1087 #define QPCR_TEST_GET2 0x40
1088 #define QPCR_TEST_FOR3 0x80
1089 #define QPCR_TEST_GET3 0x40
1090 #define QPCR_TEST_FOR4 0xC0
1091 #define QPCR_TEST_GET4 0x80
1093 #define QOPR_CLOCK_X1 0x0000
1094 #define QOPR_CLOCK_X2 0x0001
1095 #define QOPR_CLOCK_X4 0x0002
1096 #define QOPR_CLOCK_X8 0x0003
1097 #define QOPR_CLOCK_RATE_MASK 0x0003
1103 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1105 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1112 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1113 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1114 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1115 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1116 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1117 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1118 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1119 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1120 { 0, }
1125 struct quatech_feature *qf = &quatech_cards[0]; in pci_quatech_amcc()
1131 pr_err("quatech: unknown port type '0x%04X'.\n", devid); in pci_quatech_amcc()
1132 return 0; in pci_quatech_amcc()
1141 outb(0xBF, base + UART_LCR); in pci_quatech_rqopr()
1153 outb(0xBF, base + UART_LCR); in pci_quatech_wqopr()
1165 outb(0xBF, base + UART_LCR); in pci_quatech_rqmcr()
1167 outb(val | 0x10, base + UART_SCR); in pci_quatech_rqmcr()
1181 outb(0xBF, base + UART_LCR); in pci_quatech_wqmcr()
1183 outb(val | 0x10, base + UART_SCR); in pci_quatech_wqmcr()
1195 outb(0xBF, base + UART_LCR); in pci_quatech_has_qmcr()
1197 if (val & 0x20) { in pci_quatech_has_qmcr()
1198 outb(0x80, UART_LCR); in pci_quatech_has_qmcr()
1199 if (!(inb(UART_SCR) & 0x20)) { in pci_quatech_has_qmcr()
1204 return 0; in pci_quatech_has_qmcr()
1213 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1217 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1221 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1225 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1230 return 0; in pci_quatech_test()
1238 if (pci_quatech_test(port) < 0) in pci_quatech_clock()
1280 int rs422 = 0; in pci_quatech_rs422()
1283 return 0; in pci_quatech_rs422()
1285 pci_quatech_wqmcr(port, 0xFF); in pci_quatech_rs422()
1295 unsigned long base = pci_resource_start(dev, 0); in pci_quatech_init()
1299 outl(inl(base + 0x38) | 0x00002000, base + 0x38); in pci_quatech_init()
1300 tmp = inl(base + 0x3c); in pci_quatech_init()
1301 outl(tmp | 0x01000000, base + 0x3c); in pci_quatech_init()
1302 outl(tmp &= ~0x01000000, base + 0x3c); in pci_quatech_init()
1305 return 0; in pci_quatech_init()
1363 serial_port_out(port, UART_LCR, lcr | 0x80); in pericom_do_set_divisor()
1366 serial_port_out(port, UART_DLM, 0); in pericom_do_set_divisor()
1413 offset = 0x38; in pci_pericom_setup_four_at_eight()
1433 ret = setup_port(priv, port, idx, 0, board->reg_shift); in ce4100_serial_setup()
1447 return setup_port(priv, port, 2, idx * 8, 0); in pci_omegapci_setup()
1462 /* RTS will control by MCR if this bit is 0 */
1475 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); in pci_fintek_rs485_config()
1480 memset(rs485->padding, 0, sizeof(rs485->padding)); in pci_fintek_rs485_config()
1482 memset(rs485, 0, sizeof(*rs485)); in pci_fintek_rs485_config()
1499 rs485->delay_rts_after_send = 0; in pci_fintek_rs485_config()
1500 rs485->delay_rts_before_send = 0; in pci_fintek_rs485_config()
1506 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); in pci_fintek_rs485_config()
1511 return 0; in pci_fintek_rs485_config()
1523 config_base = 0x40 + 0x08 * idx; in pci_fintek_setup()
1528 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); in pci_fintek_setup()
1542 return 0; in pci_fintek_setup()
1560 case 0x1104: /* 4 ports */ in pci_fintek_init()
1561 case 0x1108: /* 8 ports */ in pci_fintek_init()
1562 max_port = dev->device & 0xff; in pci_fintek_init()
1564 case 0x1112: /* 12 ports */ in pci_fintek_init()
1572 bar_data[0] = pci_resource_start(dev, 5); in pci_fintek_init()
1576 for (i = 0; i < max_port; ++i) { in pci_fintek_init()
1577 /* UART0 configuration offset start from 0x40 */ in pci_fintek_init()
1578 config_base = 0x40 + 0x08 * i; in pci_fintek_init()
1581 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; in pci_fintek_init()
1584 pci_write_config_byte(dev, config_base + 0x00, 0x01); in pci_fintek_init()
1587 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_init()
1590 pci_write_config_byte(dev, config_base + 0x04, in pci_fintek_init()
1591 (u8)(iobase & 0xff)); in pci_fintek_init()
1594 pci_write_config_byte(dev, config_base + 0x05, in pci_fintek_init()
1595 (u8)((iobase & 0xff00) >> 8)); in pci_fintek_init()
1597 pci_write_config_byte(dev, config_base + 0x06, dev->irq); in pci_fintek_init()
1609 pci_write_config_byte(dev, config_base + 0x07, 0x01); in pci_fintek_init()
1644 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; in pci_fintek_f815xxa_setup()
1647 return 0; in pci_fintek_f815xxa_setup()
1655 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) in pci_fintek_f815xxa_init()
1659 case 0x1204: /* 4 ports */ in pci_fintek_f815xxa_init()
1660 case 0x1208: /* 8 ports */ in pci_fintek_f815xxa_init()
1661 max_port = dev->device & 0xff; in pci_fintek_f815xxa_init()
1663 case 0x1212: /* 12 ports */ in pci_fintek_f815xxa_init()
1671 pci_write_config_byte(dev, 0x209, 0x40); in pci_fintek_f815xxa_init()
1673 for (i = 0; i < max_port; ++i) { in pci_fintek_f815xxa_init()
1674 /* UART0 configuration offset start from 0x2A0 */ in pci_fintek_f815xxa_init()
1675 config_base = 0x2A0 + 0x08 * i; in pci_fintek_f815xxa_init()
1678 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_f815xxa_init()
1681 pci_write_config_byte(dev, config_base + 0, 0x01); in pci_fintek_f815xxa_init()
1718 * port registers could return 0 momentarily. Functions like in kt_serial_in()
1721 * setting IER register inadvertently to 0, if the value read in kt_serial_in()
1722 * is 0, double check with ier value in uart_8250_port and use in kt_serial_in()
1728 if (val == 0) in kt_serial_in()
1749 return 0; in pci_eg20t_init()
1784 #define CH384_XINT_ENABLE_REG 0xEB
1785 #define CH384_XINT_ENABLE_BIT 0x02
1794 case 0x3853: /* 8 ports */ in pci_wch_ch38x_init()
1801 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_init()
1811 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_exit()
1812 outb(0x0, iobase + CH384_XINT_ENABLE_REG); in pci_wch_ch38x_exit()
1828 bar = 0; in pci_sunix_setup()
1837 return setup_port(priv, port, bar, offset, 0); in pci_sunix_setup()
1853 return setup_port(priv, port, bar, offset, 0); in pci_moxa_setup()
1856 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1857 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1858 #define PCI_DEVICE_ID_OCTPRO 0x0001
1859 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1860 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1861 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1862 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1863 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1864 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1865 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1866 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1867 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1868 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1869 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1870 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1871 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1872 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1873 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1874 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1875 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1876 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1877 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1878 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1879 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1880 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1881 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1882 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1883 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1884 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1885 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1886 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1887 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1888 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1889 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1890 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1891 #define PCI_VENDOR_ID_WCH 0x4348
1892 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1893 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1894 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1895 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1896 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1897 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1898 #define PCI_VENDOR_ID_AGESTAR 0x5372
1899 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1900 #define PCI_VENDOR_ID_ASIX 0x9710
1901 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1902 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1904 #define PCIE_VENDOR_ID_WCH 0x1c00
1905 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1906 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1907 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1908 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1910 #define PCI_VENDOR_ID_ACCESIO 0x494f
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1912 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1914 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1916 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1918 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1920 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1921 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1922 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1923 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1924 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1925 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1926 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1927 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1928 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1929 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1930 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1931 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1932 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1933 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1934 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1935 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1936 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1937 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1938 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1939 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1940 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1941 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1942 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1943 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1946 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1947 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1948 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1949 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1950 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1951 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1952 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1953 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1954 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1955 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1956 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1957 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1960 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1961 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2020 .subvendor = 0xe4bf,
2541 .device = 0x8811,
2549 .device = 0x8812,
2557 .device = 0x8813,
2565 .device = 0x8814,
2572 .vendor = 0x10DB,
2573 .device = 0x8027,
2580 .vendor = 0x10DB,
2581 .device = 0x8028,
2588 .vendor = 0x10DB,
2589 .device = 0x8029,
2596 .vendor = 0x10DB,
2597 .device = 0x800C,
2604 .vendor = 0x10DB,
2605 .device = 0x800D,
2724 .vendor = 0x1c29,
2725 .device = 0x1104,
2732 .vendor = 0x1c29,
2733 .device = 0x1108,
2740 .vendor = 0x1c29,
2741 .device = 0x1112,
2758 .vendor = 0x1c29,
2759 .device = 0x1204,
2766 .vendor = 0x1c29,
2767 .device = 0x1208,
2774 .vendor = 0x1c29,
2775 .device = 0x1212,
2833 pbn_default = 0,
2989 * offset 0x10 from the UART base, while UART_IER is defined as 1
3430 .uart_offset = 0x400,
3437 .uart_offset = 0x400,
3444 .uart_offset = 0x400,
3455 .first_offset = 0x03,
3460 * Uses the size of PCI Base region 0 to
3468 .uart_offset = 0x200,
3469 .first_offset = 0x1000,
3473 * This board uses the size of PCI Base region 0 to
3486 .uart_offset = 0x200,
3487 .first_offset = 0x1000,
3493 .uart_offset = 0x200,
3494 .first_offset = 0x1000,
3500 .uart_offset = 0x200,
3501 .first_offset = 0x1000,
3507 .uart_offset = 0x200,
3508 .first_offset = 0x1000,
3522 .first_offset = 0x10000,
3529 .reg_shift = 0,
3530 .first_offset = 0x20178,
3540 .uart_offset = 0x40,
3542 .first_offset = 0x200,
3548 .uart_offset = 0x40,
3550 .first_offset = 0x200,
3556 .uart_offset = 0x40,
3558 .first_offset = 0x200,
3582 .uart_offset = 0x10,
3583 .first_offset = 0x800,
3589 .uart_offset = 0x10,
3590 .first_offset = 0x800,
3596 .uart_offset = 0x10,
3597 .first_offset = 0x800,
3603 .uart_offset = 0x10,
3604 .first_offset = 0x800,
3613 .uart_offset = 0x200,
3614 .first_offset = 0x1000,
3620 .uart_offset = 0x200,
3621 .first_offset = 0x1000,
3627 .uart_offset = 0x200,
3628 .first_offset = 0x1000,
3634 .uart_offset = 0x200,
3635 .first_offset = 0x1000,
3647 .uart_offset = 0x200,
3664 .first_offset = 0x40,
3670 .first_offset = 0x40,
3676 .first_offset = 0x40,
3698 .first_offset = 0xC0,
3705 .first_offset = 0xC0,
3712 .first_offset = 0x00,
3721 .uart_offset = 0x8,
3727 .uart_offset = 0x8,
3733 .uart_offset = 0x8,
3739 .uart_offset = 0x8,
3744 .uart_offset = 0x8,
3749 .uart_offset = 0x8,
3754 .uart_offset = 0x8,
3759 .uart_offset = 0x8,
3764 .uart_offset = 0x8,
3770 .uart_offset = 0x200,
3771 .first_offset = 0x1000,
3777 .uart_offset = 0x200,
3778 .first_offset = 0x1000,
3784 .uart_offset = 0x200,
3785 .first_offset = 0x1000,
3791 .uart_offset = 0x200,
3792 .first_offset = 0x1000,
3798 .uart_offset = 0x200,
3804 .uart_offset = 0x200,
3810 .uart_offset = 0x200,
3816 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3817 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3818 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3821 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3822 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3823 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3826 { PCI_VDEVICE(INTEL, 0x081b), },
3827 { PCI_VDEVICE(INTEL, 0x081c), },
3828 { PCI_VDEVICE(INTEL, 0x081d), },
3829 { PCI_VDEVICE(INTEL, 0x1191), },
3830 { PCI_VDEVICE(INTEL, 0x18d8), },
3831 { PCI_VDEVICE(INTEL, 0x19d8), },
3834 { PCI_VDEVICE(INTEL, 0x0936), },
3835 { PCI_VDEVICE(INTEL, 0x0f0a), },
3836 { PCI_VDEVICE(INTEL, 0x0f0c), },
3837 { PCI_VDEVICE(INTEL, 0x228a), },
3838 { PCI_VDEVICE(INTEL, 0x228c), },
3839 { PCI_VDEVICE(INTEL, 0x4b96), },
3840 { PCI_VDEVICE(INTEL, 0x4b97), },
3841 { PCI_VDEVICE(INTEL, 0x4b98), },
3842 { PCI_VDEVICE(INTEL, 0x4b99), },
3843 { PCI_VDEVICE(INTEL, 0x4b9a), },
3844 { PCI_VDEVICE(INTEL, 0x4b9b), },
3845 { PCI_VDEVICE(INTEL, 0x9ce3), },
3846 { PCI_VDEVICE(INTEL, 0x9ce4), },
3865 (dev->class & 0xff) > 6) in serial_pci_is_class_communication()
3868 return 0; in serial_pci_is_class_communication()
3874 * serial specs. Returns 0 on success, -ENODEV on failure.
3892 num_iomem = num_port = 0; in serial_pci_guess_board()
3893 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
3904 * If there is 1 or 0 iomem regions, and exactly one port, in serial_pci_guess_board()
3911 return 0; in serial_pci_guess_board()
3920 num_port = 0; in serial_pci_guess_board()
3921 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
3934 return 0; in serial_pci_guess_board()
3970 * <0 - error in pciserial_init_ports()
3971 * 0 - use board->num_ports in pciserial_init_ports()
3972 * >0 - number of ports in pciserial_init_ports()
3976 if (rc < 0) { in pciserial_init_ports()
3995 memset(&uart, 0, sizeof(uart)); in pciserial_init_ports()
4000 uart.port.irq = 0; in pciserial_init_ports()
4011 if (rc < 0) { in pciserial_init_ports()
4017 uart.port.irq = pci_irq_vector(dev, 0); in pciserial_init_ports()
4022 for (i = 0; i < nr_ports; i++) { in pciserial_init_ports()
4030 if (priv->line[i] < 0) { in pciserial_init_ports()
4055 for (i = 0; i < priv->nr; i++) in pciserial_detach_ports()
4077 for (i = 0; i < priv->nr; i++) in pciserial_suspend_ports()
4078 if (priv->line[i] >= 0) in pciserial_suspend_ports()
4099 for (i = 0; i < priv->nr; i++) in pciserial_resume_ports()
4100 if (priv->line[i] >= 0) in pciserial_resume_ports()
4167 if (rc == 0 && serial_pci_matches(board, &tmp)) in pciserial_init_one()
4177 return 0; in pciserial_init_one()
4195 return 0; in pciserial_suspend_one()
4214 return 0; in pciserial_resume_one()
4222 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4224 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4226 /* Advantech also use 0x3618 and 0xf618 */
4228 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4231 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4255 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4259 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4263 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4267 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4271 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4275 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4279 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4283 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4287 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4291 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4295 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4299 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4303 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 /* Unknown card - subdevice 0x1584 */
4348 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4350 /* Unknown card - subdevice 0x1588 */
4353 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4357 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4371 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4375 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4379 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4383 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4387 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4391 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4395 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4402 0x10b5, 0x106a, 0, 0,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 0, 0,
4481 0, 0,
4483 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 * For now just used the hex ID 0x950a.
4493 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4495 0, 0, pbn_b0_2_115200 },
4496 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4498 0, 0, pbn_b0_2_115200 },
4499 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4654 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4656 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4657 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4659 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4660 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4662 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4663 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4670 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4678 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4681 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4684 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4687 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 0, 0, pbn_computone_4 },
4849 0, 0, pbn_computone_8 },
4852 0, 0, pbn_computone_6 },
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4865 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4868 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4871 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4874 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4877 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4880 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4883 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 * ACR = 0x10, and as such are not currently fully supported.
4942 0x1204, 0x0004, 0, 0,
4945 0x1208, 0x0004, 0, 0,
4948 0x1402, 0x0002, 0, 0,
4951 0x1404, 0x0004, 0, 0,
4954 0x1208, 0x0004, 0, 0,
4958 0x1204, 0x0004, 0, 0,
4961 0x1208, 0x0004, 0, 0,
4964 0x1208, 0x0004, 0, 0,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991 0xE4BF, PCI_ANY_ID, 0, 0,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5015 0x1048, 0x1500, 0, 0,
5019 0xFF00, 0, 0, 0,
5026 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 0,
5054 0, pbn_pericom_PI7C9X7951 },
5057 0,
5058 0, pbn_pericom_PI7C9X7952 },
5061 0,
5062 0, pbn_pericom_PI7C9X7954 },
5065 0,
5066 0, pbn_pericom_PI7C9X7958 },
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5180 0, 0,
5187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5198 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5200 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5202 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5204 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5211 0, 0, pbn_b2_4_921600 },
5214 0, 0, pbn_b2_8_921600 },
5224 PCI_VENDOR_ID_MAINPINE, 0x0200,
5225 0, 0, pbn_b0_2_115200 },
5228 PCI_VENDOR_ID_MAINPINE, 0x0300,
5229 0, 0, pbn_b0_4_115200 },
5232 PCI_VENDOR_ID_MAINPINE, 0x0400,
5233 0, 0, pbn_b0_2_115200 },
5236 PCI_VENDOR_ID_MAINPINE, 0x0500,
5237 0, 0, pbn_b0_4_115200 },
5240 PCI_VENDOR_ID_MAINPINE, 0x0600,
5241 0, 0, pbn_b0_2_115200 },
5244 PCI_VENDOR_ID_MAINPINE, 0x0700,
5245 0, 0, pbn_b0_4_115200 },
5248 PCI_VENDOR_ID_MAINPINE, 0x0800,
5249 0, 0, pbn_b0_8_115200 },
5252 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5253 0, 0, pbn_b0_2_115200 },
5256 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5257 0, 0, pbn_b0_4_115200 },
5260 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5261 0, 0, pbn_b0_8_115200 },
5264 PCI_VENDOR_ID_MAINPINE, 0x2000,
5265 0, 0, pbn_b0_1_115200 },
5268 PCI_VENDOR_ID_MAINPINE, 0x2100,
5269 0, 0, pbn_b0_1_115200 },
5272 PCI_VENDOR_ID_MAINPINE, 0x2200,
5273 0, 0, pbn_b0_2_115200 },
5276 PCI_VENDOR_ID_MAINPINE, 0x2300,
5277 0, 0, pbn_b0_2_115200 },
5280 PCI_VENDOR_ID_MAINPINE, 0x2400,
5281 0, 0, pbn_b0_4_115200 },
5284 PCI_VENDOR_ID_MAINPINE, 0x2500,
5285 0, 0, pbn_b0_4_115200 },
5288 PCI_VENDOR_ID_MAINPINE, 0x2600,
5289 0, 0, pbn_b0_8_115200 },
5292 PCI_VENDOR_ID_MAINPINE, 0x2700,
5293 0, 0, pbn_b0_8_115200 },
5296 PCI_VENDOR_ID_MAINPINE, 0x3000,
5297 0, 0, pbn_b0_1_115200 },
5300 PCI_VENDOR_ID_MAINPINE, 0x3100,
5301 0, 0, pbn_b0_1_115200 },
5304 PCI_VENDOR_ID_MAINPINE, 0x3200,
5305 0, 0, pbn_b0_2_115200 },
5308 PCI_VENDOR_ID_MAINPINE, 0x3300,
5309 0, 0, pbn_b0_2_115200 },
5312 PCI_VENDOR_ID_MAINPINE, 0x3400,
5313 0, 0, pbn_b0_4_115200 },
5316 PCI_VENDOR_ID_MAINPINE, 0x3500,
5317 0, 0, pbn_b0_4_115200 },
5320 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5321 0, 0, pbn_b0_8_115200 },
5324 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5325 0, 0, pbn_b0_8_115200 },
5331 { PCI_VENDOR_ID_PASEMI, 0xa004,
5332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5458 0,
5459 0,
5466 0,
5467 0,
5474 0,
5475 0,
5482 0,
5483 0,
5490 0,
5491 0,
5498 0,
5499 0,
5506 0,
5507 0,
5514 0,
5515 0,
5522 0,
5523 0,
5530 0,
5531 0,
5538 0,
5539 0,
5546 0,
5547 0,
5554 0,
5555 0,
5562 0,
5563 0,
5570 0,
5571 0,
5575 PCI_VENDOR_ID_IBM, 0x0299,
5576 0, 0, pbn_b0_bt_2_115200 },
5585 0xA000, 0x1000,
5586 0, 0, pbn_b0_1_115200 },
5590 0xA000, 0x1000,
5591 0, 0, pbn_b0_1_115200 },
5594 0xA000, 0x1000,
5595 0, 0, pbn_b0_1_115200 },
5598 0xA000, 0x1000,
5599 0, 0, pbn_b0_1_115200 },
5602 0xA000, 0x1000,
5603 0, 0, pbn_b0_1_115200 },
5606 0xA000, 0x3002,
5607 0, 0, pbn_NETMOS9900_2s_115200 },
5614 0xA000, 0x1000,
5615 0, 0, pbn_b0_1_115200 },
5618 0xA000, 0x3002,
5619 0, 0, pbn_b0_bt_2_115200 },
5622 0xA000, 0x3004,
5623 0, 0, pbn_b0_bt_4_115200 },
5626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5648 0, 0, pbn_b0_bt_2_115200 },
5656 0, 0, pbn_b0_bt_4_115200 },
5660 0, 0, pbn_b0_bt_2_115200 },
5664 0, 0, pbn_b0_bt_4_115200 },
5668 0, 0, pbn_wch382_2 },
5672 0, 0, pbn_wch384_4 },
5676 0, 0, pbn_wch384_8 },
5680 { PCI_VENDOR_ID_REALTEK, 0x816a,
5682 0, 0, pbn_b0_1_115200 },
5684 { PCI_VENDOR_ID_REALTEK, 0x816b,
5686 0, 0, pbn_b0_1_115200 },
5689 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5690 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5691 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5692 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5693 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5694 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5697 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5698 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5701 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5710 0xffff00, pbn_default },
5714 0xffff00, pbn_default },
5718 0xffff00, pbn_default },
5719 { 0, }