1 // SPDX-License-Identifier: GPL-2.0
32 		writeb(value, p->membase);  in serial8250_em_serial_out()
38 		writel(value, p->membase + ((offset + 1) << 2));  in serial8250_em_serial_out()
41 		value &= 0x0f; /* only 4 valid bits - not Xscale */  in serial8250_em_serial_out()
45 		writel(value, p->membase + (offset << 2));  in serial8250_em_serial_out()
53 		return readb(p->membase);  in serial8250_em_serial_in()
58 		return readl(p->membase + ((offset + 1) << 2));  in serial8250_em_serial_in()
63 		return readl(p->membase + (offset << 2));  in serial8250_em_serial_in()
92 		dev_err(&pdev->dev, "missing registers\n");  in serial8250_em_probe()
93 		return -EINVAL;  in serial8250_em_probe()
96 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in serial8250_em_probe()
98 		return -ENOMEM;  in serial8250_em_probe()
100 	priv->sclk = devm_clk_get(&pdev->dev, "sclk");  in serial8250_em_probe()
101 	if (IS_ERR(priv->sclk)) {  in serial8250_em_probe()
102 		dev_err(&pdev->dev, "unable to get clock\n");  in serial8250_em_probe()
103 		return PTR_ERR(priv->sclk);  in serial8250_em_probe()
107 	up.port.mapbase = regs->start;  in serial8250_em_probe()
111 	up.port.dev = &pdev->dev;  in serial8250_em_probe()
114 	clk_prepare_enable(priv->sclk);  in serial8250_em_probe()
115 	up.port.uartclk = clk_get_rate(priv->sclk);  in serial8250_em_probe()
125 		dev_err(&pdev->dev, "unable to register 8250 port\n");  in serial8250_em_probe()
126 		clk_disable_unprepare(priv->sclk);  in serial8250_em_probe()
130 	priv->line = ret;  in serial8250_em_probe()
139 	serial8250_unregister_port(priv->line);  in serial8250_em_remove()
140 	clk_disable_unprepare(priv->sclk);  in serial8250_em_remove()
145 	{ .compatible = "renesas,em-uart", },
152 		.name		= "serial8250-em",