Lines Matching +full:0 +full:x740
29 TB_SWITCH_CAP_TMU = 0x03,
30 TB_SWITCH_CAP_VSE = 0x05,
34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
35 TB_VSE_CAP_TIME2 = 0x03,
36 TB_VSE_CAP_IECS = 0x04,
37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
41 TB_PORT_CAP_PHY = 0x01,
42 TB_PORT_CAP_POWER = 0x02,
43 TB_PORT_CAP_TIME1 = 0x03,
44 TB_PORT_CAP_ADAP = 0x04,
45 TB_PORT_CAP_VSE = 0x05,
46 TB_PORT_CAP_USB4 = 0x06,
50 TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
61 u8 cap; /* if cap == 0x05 then we have a extended capability */
137 bool access_low:1; /* set to 0 before access */
141 bool not_present:1; /* should be 0 */
161 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
163 /* DWORD 0 */
181 * milliseconds. Writing 0x00 is interpreted
190 #define USB4_VERSION_1_0 0x20
192 #define ROUTER_CS_1 0x01
193 #define ROUTER_CS_4 0x04
194 #define ROUTER_CS_5 0x05
195 #define ROUTER_CS_5_SLP BIT(0)
204 #define ROUTER_CS_6 0x06
205 #define ROUTER_CS_6_SLPR BIT(0)
211 #define ROUTER_CS_7 0x07
212 #define ROUTER_CS_9 0x09
213 #define ROUTER_CS_25 0x19
214 #define ROUTER_CS_26 0x1a
215 #define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0)
223 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
224 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
225 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
226 USB4_SWITCH_OP_NVM_WRITE = 0x20,
227 USB4_SWITCH_OP_NVM_AUTH = 0x21,
228 USB4_SWITCH_OP_NVM_READ = 0x22,
229 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
230 USB4_SWITCH_OP_DROM_READ = 0x24,
231 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
232 USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,
236 #define TMU_RTR_CS_0 0x00
239 #define TMU_RTR_CS_1 0x01
242 #define TMU_RTR_CS_2 0x02
243 #define TMU_RTR_CS_3 0x03
244 #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
247 #define TMU_RTR_CS_22 0x16
248 #define TMU_RTR_CS_24 0x18
251 TB_TYPE_INACTIVE = 0x000000,
252 TB_TYPE_PORT = 0x000001,
253 TB_TYPE_NHI = 0x000002,
254 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
255 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */
256 TB_TYPE_DP_HDMI_IN = 0x0e0101,
257 TB_TYPE_DP_HDMI_OUT = 0x0e0102,
258 TB_TYPE_PCIE_DOWN = 0x100101,
259 TB_TYPE_PCIE_UP = 0x100102,
260 TB_TYPE_USB3_DOWN = 0x200101,
261 TB_TYPE_USB3_UP = 0x200102,
266 /* DWORD 0 */
296 #define ADP_CS_4 0x04
297 #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
301 #define ADP_CS_5 0x05
306 #define TMU_ADP_CS_3 0x03
310 #define LANE_ADP_CS_0 0x00
313 #define LANE_ADP_CS_1 0x01
316 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
317 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
322 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
323 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
328 #define PORT_CS_1 0x01
337 #define PORT_CS_2 0x02
338 #define PORT_CS_18 0x12
342 #define PORT_CS_19 0x13
350 #define ADP_DP_CS_0 0x00
355 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
358 #define ADP_DP_CS_2 0x02
360 #define ADP_DP_CS_3 0x03
362 #define DP_LOCAL_CAP 0x04
363 #define DP_REMOTE_CAP 0x05
364 #define DP_STATUS_CTRL 0x06
367 #define DP_COMMON_CAP 0x07
374 #define DP_COMMON_CAP_RATE_RBR 0x0
375 #define DP_COMMON_CAP_RATE_HBR 0x1
376 #define DP_COMMON_CAP_RATE_HBR2 0x2
377 #define DP_COMMON_CAP_RATE_HBR3 0x3
380 #define DP_COMMON_CAP_1_LANE 0x0
381 #define DP_COMMON_CAP_2_LANES 0x1
382 #define DP_COMMON_CAP_4_LANES 0x2
386 #define ADP_PCIE_CS_0 0x00
390 #define ADP_USB3_CS_0 0x00
393 #define ADP_USB3_CS_1 0x01
394 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
398 #define ADP_USB3_CS_2 0x02
399 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
403 #define ADP_USB3_CS_3 0x03
404 #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
405 #define ADP_USB3_CS_4 0x04
406 #define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0)
407 #define ADP_USB3_CS_4_ALR_20G 0x1
411 #define ADP_USB3_CS_4_MSLR_20G 0x1
415 /* DWORD 0 */
441 #define TB_LC_DESC 0x02
442 #define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
447 #define TB_LC_FUSE 0x03
448 #define TB_LC_SNK_ALLOCATION 0x10
449 #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
450 #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
453 #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
454 #define TB_LC_POWER 0x740
457 #define TB_LC_PORT_ATTR 0x8d
460 #define TB_LC_SX_CTRL 0x96