20 	return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);  in tb_lc_read_uuid()
27 	return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);  in read_lc_desc()
62 	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_set_port_configured()
82 	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_set_port_configured()
120 	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_set_xdomain_configured()
135 	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_set_xdomain_configured()
187 	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_start_lane_initialization()
193 	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);  in tb_lc_start_lane_initialization()
206 	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,  in tb_lc_set_wake_one()
223 	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);  in tb_lc_set_wake_one()
294 		ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,  in tb_lc_set_sleep()
300 		ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,  in tb_lc_set_sleep()
330 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1);  in tb_lc_lane_bonding_possible()
356 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,  in tb_lc_dp_sink_available()
431 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,  in tb_lc_dp_sink_alloc()
445 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,  in tb_lc_dp_sink_alloc()
479 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,  in tb_lc_dp_sink_dealloc()
489 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,  in tb_lc_dp_sink_dealloc()
509 	return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1);  in tb_lc_force_power()