Lines Matching +full:adc +full:- +full:channels

1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
9 #include <linux/iio/adc/qcom-vadc-common.h>
20 * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each
21 * channel is programmed to use one of ADC channels for voltage comparison.
22 * Voltages are programmed using ADC codes, so we have to convert temp to
23 * voltage and then to ADC code value.
25 * Configuration of TM channels must match configuration of corresponding ADC
26 * channels.
96 * struct adc_tm5_channel - ADC Thermal Monitoring channel data.
98 * @adc_channel: corresponding ADC channel number.
104 * @chip: ADC TM chip instance.
119 * struct adc_tm5_chip - ADC Thermal Monitoring properties
123 * @channels: array of ADC TM channel data.
124 * @nchannels: amount of channels defined/allocated
126 * @avg_samples: ability to provide single result from the ADC
134 struct adc_tm5_channel *channels; member
151 return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); in adc_tm5_read()
156 return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); in adc_tm5_write()
161 return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); in adc_tm5_reg_update()
172 dev_err(chip->dev, "read status low failed: %d\n", ret); in adc_tm5_isr()
178 dev_err(chip->dev, "read status high failed: %d\n", ret); in adc_tm5_isr()
182 for (i = 0; i < chip->nchannels; i++) { in adc_tm5_isr()
184 unsigned int ch = chip->channels[i].channel; in adc_tm5_isr()
187 if (!chip->channels[i].tzd) in adc_tm5_isr()
192 dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i); in adc_tm5_isr()
206 thermal_zone_device_update(chip->channels[i].tzd, in adc_tm5_isr()
218 if (!channel || !channel->iio) in adc_tm5_get_temp()
219 return -EINVAL; in adc_tm5_get_temp()
221 ret = iio_read_channel_processed(channel->iio, temp); in adc_tm5_get_temp()
226 return -EINVAL; in adc_tm5_get_temp()
233 struct adc_tm5_chip *chip = channel->chip; in adc_tm5_disable_channel()
234 unsigned int reg = ADC_TM5_M_EN(channel->channel); in adc_tm5_disable_channel()
251 dev_err(chip->dev, "adc-tm enable failed\n"); in adc_tm5_enable()
258 dev_err(chip->dev, "adc-tm request conversion failed\n"); in adc_tm5_enable()
267 struct adc_tm5_chip *chip = channel->chip; in adc_tm5_configure()
269 u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); in adc_tm5_configure()
274 dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret); in adc_tm5_configure()
278 buf[0] = channel->adc_channel; in adc_tm5_configure()
282 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, in adc_tm5_configure()
283 chip->data->full_scale_code_volt, high); in adc_tm5_configure()
293 if (low != -INT_MAX) { in adc_tm5_configure()
294 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, in adc_tm5_configure()
295 chip->data->full_scale_code_volt, low); in adc_tm5_configure()
308 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); in adc_tm5_configure()
310 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); in adc_tm5_configure()
316 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret); in adc_tm5_configure()
330 return -EINVAL; in adc_tm5_set_trips()
332 chip = channel->chip; in adc_tm5_set_trips()
333 dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n", in adc_tm5_set_trips()
334 channel->channel, low, high); in adc_tm5_set_trips()
336 if (high == INT_MAX && low <= -INT_MAX) in adc_tm5_set_trips()
354 for (i = 0; i < adc_tm->nchannels; i++) { in adc_tm5_register_tzd()
355 adc_tm->channels[i].chip = adc_tm; in adc_tm5_register_tzd()
357 tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, in adc_tm5_register_tzd()
358 adc_tm->channels[i].channel, in adc_tm5_register_tzd()
359 &adc_tm->channels[i], in adc_tm5_register_tzd()
362 if (PTR_ERR(tzd) == -ENODEV) { in adc_tm5_register_tzd()
363 dev_warn(adc_tm->dev, "thermal sensor on channel %d is not used\n", in adc_tm5_register_tzd()
364 adc_tm->channels[i].channel); in adc_tm5_register_tzd()
368 dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n", in adc_tm5_register_tzd()
369 adc_tm->channels[i].channel, PTR_ERR(tzd)); in adc_tm5_register_tzd()
372 adc_tm->channels[i].tzd = tzd; in adc_tm5_register_tzd()
387 dev_err(chip->dev, "read failed for BTM channels\n"); in adc_tm5_init()
391 for (i = 0; i < chip->nchannels; i++) { in adc_tm5_init()
392 if (chip->channels[i].channel >= channels_available) { in adc_tm5_init()
393 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); in adc_tm5_init()
394 return -EINVAL; in adc_tm5_init()
398 buf[0] = chip->decimation; in adc_tm5_init()
399 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; in adc_tm5_init()
406 dev_err(chip->dev, "block write failed: %d\n", ret); in adc_tm5_init()
417 const char *name = node->name; in adc_tm5_get_dt_channel_data()
420 struct device *dev = adc_tm->dev; in adc_tm5_get_dt_channel_data()
431 return -EINVAL; in adc_tm5_get_dt_channel_data()
434 channel->channel = chan; in adc_tm5_get_dt_channel_data()
437 * We are tied to PMIC's ADC controller, which always use single in adc_tm5_get_dt_channel_data()
439 * #io-channel-cells, just enforce cell_count = 1. in adc_tm5_get_dt_channel_data()
441 ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); in adc_tm5_get_dt_channel_data()
443 dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret); in adc_tm5_get_dt_channel_data()
449 dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan); in adc_tm5_get_dt_channel_data()
450 return -EINVAL; in adc_tm5_get_dt_channel_data()
452 channel->adc_channel = args.args[0]; in adc_tm5_get_dt_channel_data()
454 channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); in adc_tm5_get_dt_channel_data()
455 if (IS_ERR(channel->iio)) { in adc_tm5_get_dt_channel_data()
456 ret = PTR_ERR(channel->iio); in adc_tm5_get_dt_channel_data()
457 if (ret != -EPROBE_DEFER) in adc_tm5_get_dt_channel_data()
462 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); in adc_tm5_get_dt_channel_data()
466 dev_err(dev, "%s: invalid pre-scaling <%d %d>\n", in adc_tm5_get_dt_channel_data()
470 channel->prescale = ret; in adc_tm5_get_dt_channel_data()
473 channel->prescale = 0; in adc_tm5_get_dt_channel_data()
476 ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); in adc_tm5_get_dt_channel_data()
478 ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); in adc_tm5_get_dt_channel_data()
480 dev_err(dev, "%s invalid hw-settle-time-us %d us\n", in adc_tm5_get_dt_channel_data()
484 channel->hw_settle_time = ret; in adc_tm5_get_dt_channel_data()
486 channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; in adc_tm5_get_dt_channel_data()
490 channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; in adc_tm5_get_dt_channel_data()
492 channel->cal_method = ADC_TM5_ABSOLUTE_CAL; in adc_tm5_get_dt_channel_data()
499 struct adc_tm5_channel *channels; in adc_tm5_get_dt_data() local
503 struct device *dev = adc_tm->dev; in adc_tm5_get_dt_data()
505 adc_tm->nchannels = of_get_available_child_count(node); in adc_tm5_get_dt_data()
506 if (!adc_tm->nchannels) in adc_tm5_get_dt_data()
507 return -EINVAL; in adc_tm5_get_dt_data()
509 adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, in adc_tm5_get_dt_data()
510 sizeof(*adc_tm->channels), GFP_KERNEL); in adc_tm5_get_dt_data()
511 if (!adc_tm->channels) in adc_tm5_get_dt_data()
512 return -ENOMEM; in adc_tm5_get_dt_data()
514 channels = adc_tm->channels; in adc_tm5_get_dt_data()
516 adc_tm->data = of_device_get_match_data(dev); in adc_tm5_get_dt_data()
517 if (!adc_tm->data) in adc_tm5_get_dt_data()
518 adc_tm->data = &adc_tm5_data_pmic; in adc_tm5_get_dt_data()
522 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); in adc_tm5_get_dt_data()
527 adc_tm->decimation = ret; in adc_tm5_get_dt_data()
529 adc_tm->decimation = ADC5_DECIMATION_DEFAULT; in adc_tm5_get_dt_data()
532 ret = of_property_read_u32(node, "qcom,avg-samples", &value); in adc_tm5_get_dt_data()
536 dev_err(dev, "invalid avg-samples %d\n", value); in adc_tm5_get_dt_data()
539 adc_tm->avg_samples = ret; in adc_tm5_get_dt_data()
541 adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; in adc_tm5_get_dt_data()
545 ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); in adc_tm5_get_dt_data()
551 channels++; in adc_tm5_get_dt_data()
559 struct device_node *node = pdev->dev.of_node; in adc_tm5_probe()
560 struct device *dev = &pdev->dev; in adc_tm5_probe()
566 regmap = dev_get_regmap(dev->parent, NULL); in adc_tm5_probe()
568 return -ENODEV; in adc_tm5_probe()
574 adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); in adc_tm5_probe()
576 return -ENOMEM; in adc_tm5_probe()
578 adc_tm->regmap = regmap; in adc_tm5_probe()
579 adc_tm->dev = dev; in adc_tm5_probe()
580 adc_tm->base = reg; in adc_tm5_probe()
596 dev_err(dev, "adc-tm init failed\n"); in adc_tm5_probe()
607 IRQF_ONESHOT, "pm-adc-tm5", adc_tm); in adc_tm5_probe()
612 .compatible = "qcom,spmi-adc-tm5",
621 .name = "qcom-spmi-adc-tm5",
628 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");