29 #define AUXADC_CON1_SET_V	0x008
30 #define AUXADC_CON1_CLR_V	0x00c
31 #define AUXADC_CON2_V		0x010
32 #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
34 #define APMIXED_SYS_TS_CON1	0x604
37 #define TEMP_MONCTL0		0x000
38 #define TEMP_MONCTL1		0x004
39 #define TEMP_MONCTL2		0x008
40 #define TEMP_MONIDET0		0x014
41 #define TEMP_MONIDET1		0x018
42 #define TEMP_MSRCTL0		0x038
43 #define TEMP_MSRCTL1		0x03c
44 #define TEMP_AHBPOLL		0x040
45 #define TEMP_AHBTO		0x044
46 #define TEMP_ADCPNP0		0x048
47 #define TEMP_ADCPNP1		0x04c
48 #define TEMP_ADCPNP2		0x050
49 #define TEMP_ADCPNP3		0x0b4
51 #define TEMP_ADCMUX		0x054
52 #define TEMP_ADCEN		0x060
53 #define TEMP_PNPMUXADDR		0x064
54 #define TEMP_ADCMUXADDR		0x068
55 #define TEMP_ADCENADDR		0x074
56 #define TEMP_ADCVALIDADDR	0x078
57 #define TEMP_ADCVOLTADDR	0x07c
58 #define TEMP_RDCTRL		0x080
59 #define TEMP_ADCVALIDMASK	0x084
60 #define TEMP_ADCVOLTAGESHIFT	0x088
61 #define TEMP_ADCWRITECTRL	0x08c
62 #define TEMP_MSR0		0x090
63 #define TEMP_MSR1		0x094
64 #define TEMP_MSR2		0x098
65 #define TEMP_MSR3		0x0B8
67 #define TEMP_SPARE0		0x0f0
69 #define TEMP_ADCPNP0_1          0x148
70 #define TEMP_ADCPNP1_1          0x14c
71 #define TEMP_ADCPNP2_1          0x150
72 #define TEMP_MSR0_1             0x190
73 #define TEMP_MSR1_1             0x194
74 #define TEMP_MSR2_1             0x198
75 #define TEMP_ADCPNP3_1          0x1b4
76 #define TEMP_MSR3_1             0x1B8
78 #define PTPCORESEL		0x400
80 #define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
82 #define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
83 #define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
87 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
94 #define MT8173_TS1	0
126 #define CALIB_BUF0_VALID_V1		BIT(0)
127 #define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
128 #define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
129 #define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
130 #define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
131 #define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
132 #define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
133 #define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
134 #define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
135 #define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
136 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
137 #define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
143 #define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
144 #define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
145 #define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
146 #define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
147 #define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
148 #define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
149 #define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
150 #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
151 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
169 #define MT2701_TS1	0
189 #define MT2712_TS1	0
213 #define MT7622_TS1	0
223 #define MT8183_TS1	0
311 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
312 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
334 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
335 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
354 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
355 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
374 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
375 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
385 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
387 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
414 			.sensors = mt8173_bank_data[0],
565 	raw &= 0xfff;  in raw_to_mcelsius_v1()
585 	if (raw == 0)  in raw_to_mcelsius_v2()
586 		return 0;  in raw_to_mcelsius_v2()
588 	raw &= 0xfff;  in raw_to_mcelsius_v2()
598 	if (mt->o_slope_sign == 0)  in raw_to_mcelsius_v2()
622 		val &= ~0xf;  in mtk_thermal_get_bank()
656 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {  in mtk_thermal_bank_temperature()
673 			temp = 0;  in mtk_thermal_bank_temperature()
688 	for (i = 0; i < mt->conf->num_banks; i++) {  in mtk_read_temp()
700 	return 0;  in mtk_read_temp()
739 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
742 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
745 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
746 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
776 	/* AHB address for auxadc enable (channel 0 immediate mode selected) */  in mtk_thermal_init_bank()
789 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
796 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
802 	for (i = 0; i < conf->bank_data[num].num_sensors; i++)  in mtk_thermal_init_bank()
821 	regaddr_p = of_get_address(np, 0, &size64, NULL);  in of_get_phys_base()
832 	if (!(buf[0] & CALIB_BUF0_VALID_V1))  in mtk_thermal_extract_efuse_v1()
837 	for (i = 0; i < mt->conf->num_sensors; i++) {  in mtk_thermal_extract_efuse_v1()
840 			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
843 			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
863 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
865 	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))  in mtk_thermal_extract_efuse_v1()
866 		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
868 		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
870 	return 0;  in mtk_thermal_extract_efuse_v1()
878 	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
879 	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
880 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
881 	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
887 	return 0;  in mtk_thermal_extract_efuse_v2()
896 	int i, ret = 0;  in mtk_thermal_get_calibration_data()
900 	for (i = 0; i < mt->conf->num_sensors; i++)  in mtk_thermal_get_calibration_data()
903 	mt->o_slope = 0;  in mtk_thermal_get_calibration_data()
909 		return 0;  in mtk_thermal_get_calibration_data()
932 		ret = 0;  in mtk_thermal_get_calibration_data()
971 	tmp &= ~(0x37);  in mtk_thermal_turn_on_buffer()
972 	tmp |= 0x1;  in mtk_thermal_turn_on_buffer()
982 	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);  in mtk_thermal_release_periodic_ts()
983 	writel(0x1, mt->thermal_base + TEMP_MONCTL0);  in mtk_thermal_release_periodic_ts()
985 	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);  in mtk_thermal_release_periodic_ts()
1012 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in mtk_thermal_probe()
1025 	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);  in mtk_thermal_probe()
1031 	auxadc_base = of_iomap(auxadc, 0);  in mtk_thermal_probe()
1041 	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);  in mtk_thermal_probe()
1047 	apmixed_base = of_iomap(apmixedsys, 0);  in mtk_thermal_probe()
1078 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)  in mtk_thermal_probe()
1079 		for (i = 0; i < mt->conf->num_banks; i++)  in mtk_thermal_probe()
1085 	tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,  in mtk_thermal_probe()
1096 	return 0;  in mtk_thermal_probe()
1113 	return 0;  in mtk_thermal_remove()