1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6  * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
24 #include <linux/spi/spi-mem.h>
26 /* Generic QSPI register offsets */
119 #define GQSPI_TX_FIFO_FILL	(GQSPI_TXD_DEPTH -\
135 #define GQSPI_DEFAULT_NUM_CS	1	/* Default number of chip selects */
141  * struct zynqmp_qspi - Defines qspi driver instance
142  * @regs:		Virtual address of the QSPI controller registers
156  * @mode:		Defines the mode in which QSPI is operating
181  * zynqmp_gqspi_read - For GQSPI controller read operation
188 	return readl_relaxed(xqspi->regs + offset);  in zynqmp_gqspi_read()
192  * zynqmp_gqspi_write - For GQSPI controller write operation
200 	writel_relaxed(val, (xqspi->regs + offset));  in zynqmp_gqspi_write()
204  * zynqmp_gqspi_selectslave - For selection of slave device
207  * @slavebus:	To check which bus is selected- upper or lower
220 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |  in zynqmp_gqspi_selectslave()
224 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;  in zynqmp_gqspi_selectslave()
227 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;  in zynqmp_gqspi_selectslave()
230 		dev_warn(instanceptr->dev, "Invalid slave select\n");  in zynqmp_gqspi_selectslave()
236 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |  in zynqmp_gqspi_selectslave()
240 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;  in zynqmp_gqspi_selectslave()
243 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;  in zynqmp_gqspi_selectslave()
246 		dev_warn(instanceptr->dev, "Invalid slave bus\n");  in zynqmp_gqspi_selectslave()
251  * zynqmp_qspi_init_hw - Initialize the hardware
254  * The default settings of the QSPI controller's configurable parameters on
256  *	- Master mode
257  *	- TX threshold set to 1
258  *	- RX threshold set to 1
259  *	- Flash memory interface mode enabled
261  *	- Disable and clear all the interrupts
262  *	- Enable manual slave select
263  *	- Enable manual start
264  *	- Deselect all the chip select lines
265  *	- Set the little endian mode of TX FIFO and
266  *	- Enable the QSPI controller
302 	/* Clear pre-scalar by default */  in zynqmp_qspi_init_hw()
339  * zynqmp_qspi_copy_read_data - Copy data to RX buffer
347 	memcpy(xqspi->rxbuf, &data, size);  in zynqmp_qspi_copy_read_data()
348 	xqspi->rxbuf += size;  in zynqmp_qspi_copy_read_data()
349 	xqspi->bytes_to_receive -= size;  in zynqmp_qspi_copy_read_data()
353  * zynqmp_qspi_chipselect - Select or deselect the chip select line
354  * @qspi:	Pointer to the spi_device structure
355  * @is_high:	Select(0) or deselect (1) the chip select line
357 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)  in zynqmp_qspi_chipselect()  argument
359 	struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);  in zynqmp_qspi_chipselect()
366 		xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;  in zynqmp_qspi_chipselect()
367 		xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;  in zynqmp_qspi_chipselect()
368 		genfifoentry |= xqspi->genfifobus;  in zynqmp_qspi_chipselect()
369 		genfifoentry |= xqspi->genfifocs;  in zynqmp_qspi_chipselect()
395 		dev_err(xqspi->dev, "Chip select timed out\n");  in zynqmp_qspi_chipselect()
399  * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
401  * @spimode:	spimode - SPI or DUAL or QUAD.
420 		dev_warn(xqspi->dev, "Invalid SPI mode\n");  in zynqmp_qspi_selectspimode()
427  * zynqmp_qspi_config_op - Configure QSPI controller for specified
430  * @qspi:	Pointer to the spi_device structure
432  * Sets the operational mode of QSPI controller for the next QSPI transfer and
439  *	obtained using the pre-scalar value, the driver sets the clock
444  *	by the QSPI controller the driver will set the highest or lowest
448 				 struct spi_device *qspi)  in zynqmp_qspi_config_op()  argument
455 	clk_rate = clk_get_rate(xqspi->refclk);  in zynqmp_qspi_config_op()
459 		(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)  in zynqmp_qspi_config_op()
464 	/* Set the QSPI clock phase and clock polarity */  in zynqmp_qspi_config_op()
467 	if (qspi->mode & SPI_CPHA)  in zynqmp_qspi_config_op()
469 	if (qspi->mode & SPI_CPOL)  in zynqmp_qspi_config_op()
479  * zynqmp_qspi_setup_op - Configure the QSPI controller
480  * @qspi:	Pointer to the spi_device structure
482  * Sets the operational mode of QSPI controller for the next QSPI transfer,
483  * baud rate and divisor value to setup the requested qspi clock.
487 static int zynqmp_qspi_setup_op(struct spi_device *qspi)  in zynqmp_qspi_setup_op()  argument
489 	struct spi_controller *ctlr = qspi->master;  in zynqmp_qspi_setup_op()
492 	if (ctlr->busy)  in zynqmp_qspi_setup_op()
493 		return -EBUSY;  in zynqmp_qspi_setup_op()
501  * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
511 	while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {  in zynqmp_qspi_filltxfifo()
512 		if (xqspi->bytes_to_transfer >= 4) {  in zynqmp_qspi_filltxfifo()
513 			memcpy(&intermediate, xqspi->txbuf, 4);  in zynqmp_qspi_filltxfifo()
514 			xqspi->txbuf += 4;  in zynqmp_qspi_filltxfifo()
515 			xqspi->bytes_to_transfer -= 4;  in zynqmp_qspi_filltxfifo()
518 			memcpy(&intermediate, xqspi->txbuf,  in zynqmp_qspi_filltxfifo()
519 			       xqspi->bytes_to_transfer);  in zynqmp_qspi_filltxfifo()
520 			xqspi->txbuf += xqspi->bytes_to_transfer;  in zynqmp_qspi_filltxfifo()
521 			xqspi->bytes_to_transfer = 0;  in zynqmp_qspi_filltxfifo()
522 			count += xqspi->bytes_to_transfer;  in zynqmp_qspi_filltxfifo()
529  * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
539 	while ((count < size) && (xqspi->bytes_to_receive > 0)) {  in zynqmp_qspi_readrxfifo()
540 		if (xqspi->bytes_to_receive >= 4) {  in zynqmp_qspi_readrxfifo()
541 			(*(u32 *)xqspi->rxbuf) =  in zynqmp_qspi_readrxfifo()
543 			xqspi->rxbuf += 4;  in zynqmp_qspi_readrxfifo()
544 			xqspi->bytes_to_receive -= 4;  in zynqmp_qspi_readrxfifo()
548 			count += xqspi->bytes_to_receive;  in zynqmp_qspi_readrxfifo()
550 						   xqspi->bytes_to_receive);  in zynqmp_qspi_readrxfifo()
551 			xqspi->bytes_to_receive = 0;  in zynqmp_qspi_readrxfifo()
557  * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
567 	if (xqspi->txbuf) {  in zynqmp_qspi_fillgenfifo()
571 		transfer_len = xqspi->bytes_to_transfer;  in zynqmp_qspi_fillgenfifo()
572 	} else if (xqspi->rxbuf) {  in zynqmp_qspi_fillgenfifo()
576 		if (xqspi->mode == GQSPI_MODE_DMA)  in zynqmp_qspi_fillgenfifo()
577 			transfer_len = xqspi->dma_rx_bytes;  in zynqmp_qspi_fillgenfifo()
579 			transfer_len = xqspi->bytes_to_receive;  in zynqmp_qspi_fillgenfifo()
584 		transfer_len = xqspi->bytes_to_transfer;  in zynqmp_qspi_fillgenfifo()
587 	xqspi->genfifoentry = genfifoentry;  in zynqmp_qspi_fillgenfifo()
612 				tempcount = tempcount >> 1;  in zynqmp_qspi_fillgenfifo()
624 	if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {  in zynqmp_qspi_fillgenfifo()
631  * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
641 	dma_unmap_single(xqspi->dev, xqspi->dma_addr,  in zynqmp_process_dma_irq()
642 			 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);  in zynqmp_process_dma_irq()
643 	xqspi->rxbuf += xqspi->dma_rx_bytes;  in zynqmp_process_dma_irq()
644 	xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;  in zynqmp_process_dma_irq()
645 	xqspi->dma_rx_bytes = 0;  in zynqmp_process_dma_irq()
651 	if (xqspi->bytes_to_receive > 0) {  in zynqmp_process_dma_irq()
658 		genfifoentry = xqspi->genfifoentry;  in zynqmp_process_dma_irq()
659 		genfifoentry |= xqspi->bytes_to_receive;  in zynqmp_process_dma_irq()
680  * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
702 	if (xqspi->mode == GQSPI_MODE_DMA) {  in zynqmp_qspi_irq()
723 	if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&  in zynqmp_qspi_irq()
726 		complete(&xqspi->data_completion);  in zynqmp_qspi_irq()
733  * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
740 	u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;  in zynqmp_qspi_setuprxdma()
742 	if (xqspi->bytes_to_receive < 8 ||  in zynqmp_qspi_setuprxdma()
748 		xqspi->mode = GQSPI_MODE_IO;  in zynqmp_qspi_setuprxdma()
749 		xqspi->dma_rx_bytes = 0;  in zynqmp_qspi_setuprxdma()
753 	rx_rem = xqspi->bytes_to_receive % 4;  in zynqmp_qspi_setuprxdma()
754 	rx_bytes = (xqspi->bytes_to_receive - rx_rem);  in zynqmp_qspi_setuprxdma()
756 	addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,  in zynqmp_qspi_setuprxdma()
758 	if (dma_mapping_error(xqspi->dev, addr)) {  in zynqmp_qspi_setuprxdma()
759 		dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");  in zynqmp_qspi_setuprxdma()
760 		return -ENOMEM;  in zynqmp_qspi_setuprxdma()
763 	xqspi->dma_rx_bytes = rx_bytes;  in zynqmp_qspi_setuprxdma()
764 	xqspi->dma_addr = addr;  in zynqmp_qspi_setuprxdma()
778 	xqspi->mode = GQSPI_MODE_DMA;  in zynqmp_qspi_setuprxdma()
787  * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
802 	if (xqspi->mode == GQSPI_MODE_DMA) {  in zynqmp_qspi_write_op()
808 		xqspi->mode = GQSPI_MODE_IO;  in zynqmp_qspi_write_op()
813  * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
834  * zynqmp_qspi_suspend - Suspend method for the QSPI driver
837  * This function stops the QSPI driver queue and disables the QSPI controller
844 	struct spi_controller *ctlr = xqspi->ctlr;  in zynqmp_qspi_suspend()
857  * zynqmp_qspi_resume - Resume method for the QSPI driver
860  * The function starts the QSPI driver queue and initializes the QSPI
868 	struct spi_controller *ctlr = xqspi->ctlr;  in zynqmp_qspi_resume()
878  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
889 	clk_disable_unprepare(xqspi->refclk);  in zynqmp_runtime_suspend()
890 	clk_disable_unprepare(xqspi->pclk);  in zynqmp_runtime_suspend()
896  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
908 	ret = clk_prepare_enable(xqspi->pclk);  in zynqmp_runtime_resume()
914 	ret = clk_prepare_enable(xqspi->refclk);  in zynqmp_runtime_resume()
917 		clk_disable_unprepare(xqspi->pclk);  in zynqmp_runtime_resume()
925  * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
939 				    (mem->spi->master);  in zynqmp_qspi_exec_op()
942 	u16 opcode = op->cmd.opcode;  in zynqmp_qspi_exec_op()
945 	dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",  in zynqmp_qspi_exec_op()
946 		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,  in zynqmp_qspi_exec_op()
947 		op->dummy.buswidth, op->data.buswidth);  in zynqmp_qspi_exec_op()
949 	mutex_lock(&xqspi->op_lock);  in zynqmp_qspi_exec_op()
950 	zynqmp_qspi_config_op(xqspi, mem->spi);  in zynqmp_qspi_exec_op()
951 	zynqmp_qspi_chipselect(mem->spi, false);  in zynqmp_qspi_exec_op()
952 	genfifoentry |= xqspi->genfifocs;  in zynqmp_qspi_exec_op()
953 	genfifoentry |= xqspi->genfifobus;  in zynqmp_qspi_exec_op()
955 	if (op->cmd.opcode) {  in zynqmp_qspi_exec_op()
956 		reinit_completion(&xqspi->data_completion);  in zynqmp_qspi_exec_op()
957 		xqspi->txbuf = &opcode;  in zynqmp_qspi_exec_op()
958 		xqspi->rxbuf = NULL;  in zynqmp_qspi_exec_op()
959 		xqspi->bytes_to_transfer = op->cmd.nbytes;  in zynqmp_qspi_exec_op()
960 		xqspi->bytes_to_receive = 0;  in zynqmp_qspi_exec_op()
961 		zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);  in zynqmp_qspi_exec_op()
969 		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {  in zynqmp_qspi_exec_op()
970 			err = -ETIMEDOUT;  in zynqmp_qspi_exec_op()
975 	if (op->addr.nbytes) {  in zynqmp_qspi_exec_op()
976 		xqspi->txbuf = &opaddr;  in zynqmp_qspi_exec_op()
977 		for (i = 0; i < op->addr.nbytes; i++) {  in zynqmp_qspi_exec_op()
978 			*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>  in zynqmp_qspi_exec_op()
979 					(8 * (op->addr.nbytes - i - 1));  in zynqmp_qspi_exec_op()
982 		reinit_completion(&xqspi->data_completion);  in zynqmp_qspi_exec_op()
983 		xqspi->rxbuf = NULL;  in zynqmp_qspi_exec_op()
984 		xqspi->bytes_to_transfer = op->addr.nbytes;  in zynqmp_qspi_exec_op()
985 		xqspi->bytes_to_receive = 0;  in zynqmp_qspi_exec_op()
986 		zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);  in zynqmp_qspi_exec_op()
996 		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {  in zynqmp_qspi_exec_op()
997 			err = -ETIMEDOUT;  in zynqmp_qspi_exec_op()
1002 	if (op->dummy.nbytes) {  in zynqmp_qspi_exec_op()
1003 		xqspi->txbuf = NULL;  in zynqmp_qspi_exec_op()
1004 		xqspi->rxbuf = NULL;  in zynqmp_qspi_exec_op()
1006 		 * xqspi->bytes_to_transfer here represents the dummy circles  in zynqmp_qspi_exec_op()
1009 		xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;  in zynqmp_qspi_exec_op()
1010 		xqspi->bytes_to_receive = 0;  in zynqmp_qspi_exec_op()
1012 		 * Using op->data.buswidth instead of op->dummy.buswidth here because  in zynqmp_qspi_exec_op()
1015 		zynqmp_qspi_write_op(xqspi, op->data.buswidth,  in zynqmp_qspi_exec_op()
1022 	if (op->data.nbytes) {  in zynqmp_qspi_exec_op()
1023 		reinit_completion(&xqspi->data_completion);  in zynqmp_qspi_exec_op()
1024 		if (op->data.dir == SPI_MEM_DATA_OUT) {  in zynqmp_qspi_exec_op()
1025 			xqspi->txbuf = (u8 *)op->data.buf.out;  in zynqmp_qspi_exec_op()
1026 			xqspi->rxbuf = NULL;  in zynqmp_qspi_exec_op()
1027 			xqspi->bytes_to_transfer = op->data.nbytes;  in zynqmp_qspi_exec_op()
1028 			xqspi->bytes_to_receive = 0;  in zynqmp_qspi_exec_op()
1029 			zynqmp_qspi_write_op(xqspi, op->data.buswidth,  in zynqmp_qspi_exec_op()
1040 			xqspi->txbuf = NULL;  in zynqmp_qspi_exec_op()
1041 			xqspi->rxbuf = (u8 *)op->data.buf.in;  in zynqmp_qspi_exec_op()
1042 			xqspi->bytes_to_receive = op->data.nbytes;  in zynqmp_qspi_exec_op()
1043 			xqspi->bytes_to_transfer = 0;  in zynqmp_qspi_exec_op()
1044 			err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,  in zynqmp_qspi_exec_op()
1053 			if (xqspi->mode == GQSPI_MODE_DMA) {  in zynqmp_qspi_exec_op()
1065 		    (&xqspi->data_completion, msecs_to_jiffies(1000)))  in zynqmp_qspi_exec_op()
1066 			err = -ETIMEDOUT;  in zynqmp_qspi_exec_op()
1071 	zynqmp_qspi_chipselect(mem->spi, true);  in zynqmp_qspi_exec_op()
1072 	mutex_unlock(&xqspi->op_lock);  in zynqmp_qspi_exec_op()
1088  * zynqmp_qspi_probe - Probe method for the QSPI driver
1100 	struct device *dev = &pdev->dev;  in zynqmp_qspi_probe()
1101 	struct device_node *np = dev->of_node;  in zynqmp_qspi_probe()
1103 	ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));  in zynqmp_qspi_probe()
1105 		return -ENOMEM;  in zynqmp_qspi_probe()
1108 	xqspi->dev = dev;  in zynqmp_qspi_probe()
1109 	xqspi->ctlr = ctlr;  in zynqmp_qspi_probe()
1112 	xqspi->regs = devm_platform_ioremap_resource(pdev, 0);  in zynqmp_qspi_probe()
1113 	if (IS_ERR(xqspi->regs)) {  in zynqmp_qspi_probe()
1114 		ret = PTR_ERR(xqspi->regs);  in zynqmp_qspi_probe()
1118 	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");  in zynqmp_qspi_probe()
1119 	if (IS_ERR(xqspi->pclk)) {  in zynqmp_qspi_probe()
1121 		ret = PTR_ERR(xqspi->pclk);  in zynqmp_qspi_probe()
1125 	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");  in zynqmp_qspi_probe()
1126 	if (IS_ERR(xqspi->refclk)) {  in zynqmp_qspi_probe()
1128 		ret = PTR_ERR(xqspi->refclk);  in zynqmp_qspi_probe()
1132 	ret = clk_prepare_enable(xqspi->pclk);  in zynqmp_qspi_probe()
1138 	ret = clk_prepare_enable(xqspi->refclk);  in zynqmp_qspi_probe()
1144 	init_completion(&xqspi->data_completion);  in zynqmp_qspi_probe()
1146 	mutex_init(&xqspi->op_lock);  in zynqmp_qspi_probe()
1148 	pm_runtime_use_autosuspend(&pdev->dev);  in zynqmp_qspi_probe()
1149 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);  in zynqmp_qspi_probe()
1150 	pm_runtime_set_active(&pdev->dev);  in zynqmp_qspi_probe()
1151 	pm_runtime_enable(&pdev->dev);  in zynqmp_qspi_probe()
1153 	ret = pm_runtime_get_sync(&pdev->dev);  in zynqmp_qspi_probe()
1155 		dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);  in zynqmp_qspi_probe()
1159 	/* QSPI controller initializations */  in zynqmp_qspi_probe()
1162 	xqspi->irq = platform_get_irq(pdev, 0);  in zynqmp_qspi_probe()
1163 	if (xqspi->irq <= 0) {  in zynqmp_qspi_probe()
1164 		ret = -ENXIO;  in zynqmp_qspi_probe()
1167 	ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,  in zynqmp_qspi_probe()
1168 			       0, pdev->name, xqspi);  in zynqmp_qspi_probe()
1170 		ret = -ENXIO;  in zynqmp_qspi_probe()
1175 	dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));  in zynqmp_qspi_probe()
1176 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);  in zynqmp_qspi_probe()
1177 	ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;  in zynqmp_qspi_probe()
1178 	ctlr->mem_ops = &zynqmp_qspi_mem_ops;  in zynqmp_qspi_probe()
1179 	ctlr->setup = zynqmp_qspi_setup_op;  in zynqmp_qspi_probe()
1180 	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;  in zynqmp_qspi_probe()
1181 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);  in zynqmp_qspi_probe()
1182 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |  in zynqmp_qspi_probe()
1184 	ctlr->dev.of_node = np;  in zynqmp_qspi_probe()
1185 	ctlr->auto_runtime_pm = true;  in zynqmp_qspi_probe()
1187 	ret = devm_spi_register_controller(&pdev->dev, ctlr);  in zynqmp_qspi_probe()
1189 		dev_err(&pdev->dev, "spi_register_controller failed\n");  in zynqmp_qspi_probe()
1193 	pm_runtime_mark_last_busy(&pdev->dev);  in zynqmp_qspi_probe()
1194 	pm_runtime_put_autosuspend(&pdev->dev);  in zynqmp_qspi_probe()
1199 	pm_runtime_put_sync(&pdev->dev);  in zynqmp_qspi_probe()
1200 	pm_runtime_set_suspended(&pdev->dev);  in zynqmp_qspi_probe()
1201 	pm_runtime_disable(&pdev->dev);  in zynqmp_qspi_probe()
1202 	clk_disable_unprepare(xqspi->refclk);  in zynqmp_qspi_probe()
1204 	clk_disable_unprepare(xqspi->pclk);  in zynqmp_qspi_probe()
1212  * zynqmp_qspi_remove - Remove method for the QSPI driver
1226 	clk_disable_unprepare(xqspi->refclk);  in zynqmp_qspi_remove()
1227 	clk_disable_unprepare(xqspi->pclk);  in zynqmp_qspi_remove()
1228 	pm_runtime_set_suspended(&pdev->dev);  in zynqmp_qspi_remove()
1229 	pm_runtime_disable(&pdev->dev);  in zynqmp_qspi_remove()
1235 	{ .compatible = "xlnx,zynqmp-qspi-1.0", },
1245 		.name = "zynqmp-qspi",
1254 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");