Lines Matching full:qspi
3 * TI QSPI driver
128 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
131 return readl(qspi->base + reg); in ti_qspi_read()
134 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
137 writel(val, qspi->base + reg); in ti_qspi_write()
142 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
143 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup()
148 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
152 if (!qspi->spi_max_frequency) { in ti_qspi_setup()
153 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
157 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup()
159 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; in ti_qspi_setup()
162 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); in ti_qspi_setup()
167 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", in ti_qspi_setup()
172 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", in ti_qspi_setup()
173 qspi->spi_max_frequency, clk_div); in ti_qspi_setup()
175 ret = pm_runtime_get_sync(qspi->dev); in ti_qspi_setup()
177 pm_runtime_put_noidle(qspi->dev); in ti_qspi_setup()
178 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
182 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
187 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
194 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup()
195 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
197 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) in ti_qspi_restore_ctx() argument
206 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
208 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
211 static inline u32 qspi_is_busy(struct ti_qspi *qspi) in qspi_is_busy() argument
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
219 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
222 WARN(stat & BUSY, "qspi busy\n"); in qspi_is_busy()
226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) in ti_qspi_poll_wc() argument
232 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
238 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_write_msg() argument
253 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
258 if (qspi_is_busy(qspi)) in qspi_write_msg()
263 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
264 cmd, qspi->dc, *txbuf); in qspi_write_msg()
269 writel(data, qspi->base + in qspi_write_msg()
272 writel(data, qspi->base + in qspi_write_msg()
275 writel(data, qspi->base + in qspi_write_msg()
278 writel(data, qspi->base + in qspi_write_msg()
283 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
284 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
290 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
291 cmd, qspi->dc, *txbuf); in qspi_write_msg()
292 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
295 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
296 cmd, qspi->dc, *txbuf); in qspi_write_msg()
297 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
301 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_write_msg()
302 if (ti_qspi_poll_wc(qspi)) { in qspi_write_msg()
303 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_read_msg() argument
323 cmd = qspi->cmd; in qspi_read_msg()
339 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
340 if (qspi_is_busy(qspi)) in qspi_read_msg()
363 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_read_msg()
364 if (ti_qspi_poll_wc(qspi)) { in qspi_read_msg()
365 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3); in qspi_read_msg()
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2); in qspi_read_msg()
381 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1); in qspi_read_msg()
383 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
387 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
399 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
402 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
412 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_transfer_msg() argument
418 ret = qspi_write_msg(qspi, t, count); in qspi_transfer_msg()
420 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
426 ret = qspi_read_msg(qspi, t, count); in qspi_transfer_msg()
428 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
438 struct ti_qspi *qspi = param; in ti_qspi_dma_callback() local
440 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
443 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, in ti_qspi_dma_xfer() argument
446 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
454 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
459 tx->callback_param = qspi; in ti_qspi_dma_xfer()
461 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
465 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
470 ret = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
474 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
481 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, in ti_qspi_dma_bounce_buffer() argument
484 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
495 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
499 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
508 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, in ti_qspi_dma_xfer_sg() argument
512 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
519 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); in ti_qspi_dma_xfer_sg()
530 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_enable_memory_map() local
532 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); in ti_qspi_enable_memory_map()
533 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
534 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
538 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
539 qspi->current_cs = spi->chip_select; in ti_qspi_enable_memory_map()
544 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_disable_memory_map() local
546 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); in ti_qspi_disable_memory_map()
547 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
548 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
550 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
551 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
558 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup_mmap_read() local
574 ti_qspi_write(qspi, memval, in ti_qspi_setup_mmap_read()
580 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master); in ti_qspi_adjust_op_size() local
584 if (op->addr.val < qspi->mmap_size) { in ti_qspi_adjust_op_size()
586 if (op->addr.val + op->data.nbytes > qspi->mmap_size) { in ti_qspi_adjust_op_size()
587 max_len = qspi->mmap_size - op->addr.val; in ti_qspi_adjust_op_size()
595 * Adjust size to comply with the QSPI max frame length. in ti_qspi_adjust_op_size()
610 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master); in ti_qspi_exec_mem_op() local
621 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
624 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
626 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) in ti_qspi_exec_mem_op()
631 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
637 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); in ti_qspi_exec_mem_op()
641 ret = ti_qspi_dma_bounce_buffer(qspi, from, in ti_qspi_exec_mem_op()
646 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
650 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
663 struct ti_qspi *qspi = spi_master_get_devdata(master); in ti_qspi_start_transfer_one() local
671 qspi->dc = 0; in ti_qspi_start_transfer_one()
674 qspi->dc |= QSPI_CKPHA(spi->chip_select); in ti_qspi_start_transfer_one()
676 qspi->dc |= QSPI_CKPOL(spi->chip_select); in ti_qspi_start_transfer_one()
678 qspi->dc |= QSPI_CSPOL(spi->chip_select); in ti_qspi_start_transfer_one()
686 qspi->cmd = 0; in ti_qspi_start_transfer_one()
687 qspi->cmd |= QSPI_EN_CS(spi->chip_select); in ti_qspi_start_transfer_one()
688 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
690 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
692 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
694 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
698 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
704 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); in ti_qspi_start_transfer_one()
706 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
707 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
717 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
719 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
728 struct ti_qspi *qspi; in ti_qspi_runtime_resume() local
730 qspi = dev_get_drvdata(dev); in ti_qspi_runtime_resume()
731 ti_qspi_restore_ctx(qspi); in ti_qspi_runtime_resume()
736 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi) in ti_qspi_dma_cleanup() argument
738 if (qspi->rx_bb_addr) in ti_qspi_dma_cleanup()
739 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_dma_cleanup()
740 qspi->rx_bb_addr, in ti_qspi_dma_cleanup()
741 qspi->rx_bb_dma_addr); in ti_qspi_dma_cleanup()
743 if (qspi->rx_chan) in ti_qspi_dma_cleanup()
744 dma_release_channel(qspi->rx_chan); in ti_qspi_dma_cleanup()
748 {.compatible = "ti,dra7xxx-qspi" },
749 {.compatible = "ti,am4372-qspi" },
756 struct ti_qspi *qspi; in ti_qspi_probe() local
764 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
782 qspi = spi_master_get_devdata(master); in ti_qspi_probe()
783 qspi->master = master; in ti_qspi_probe()
784 qspi->dev = &pdev->dev; in ti_qspi_probe()
785 platform_set_drvdata(pdev, qspi); in ti_qspi_probe()
808 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
816 mutex_init(&qspi->list_lock); in ti_qspi_probe()
818 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
819 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
820 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
826 qspi->ctrl_base = in ti_qspi_probe()
829 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
830 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
835 1, &qspi->ctrl_reg); in ti_qspi_probe()
843 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
844 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
845 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
854 qspi->spi_max_frequency = max_freq; in ti_qspi_probe()
859 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
860 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
861 dev_err(qspi->dev, in ti_qspi_probe()
863 qspi->rx_chan = NULL; in ti_qspi_probe()
867 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
869 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
871 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
872 dev_err(qspi->dev, in ti_qspi_probe()
874 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
877 master->dma_rx = qspi->rx_chan; in ti_qspi_probe()
878 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
880 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
883 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
884 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
885 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
888 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
889 qspi->mmap_base = NULL; in ti_qspi_probe()
893 qspi->mmap_enabled = false; in ti_qspi_probe()
894 qspi->current_cs = -1; in ti_qspi_probe()
900 ti_qspi_dma_cleanup(qspi); in ti_qspi_probe()
910 struct ti_qspi *qspi = platform_get_drvdata(pdev); in ti_qspi_remove() local
913 rc = spi_master_suspend(qspi->master); in ti_qspi_remove()
920 ti_qspi_dma_cleanup(qspi); in ti_qspi_remove()
933 .name = "ti-qspi",
943 MODULE_DESCRIPTION("TI QSPI controller driver");
944 MODULE_ALIAS("platform:ti-qspi");