Lines Matching +full:tx +full:- +full:clk +full:- +full:tap +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk.h>
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
139 struct clk *clk; member
192 return readl(tqspi->base + offset); in tegra_qspi_readl()
197 writel(value, tqspi->base + offset); in tegra_qspi_writel()
201 readl(tqspi->base + QSPI_COMMAND1); in tegra_qspi_writel()
228 unsigned int remain_len = t->len - tqspi->cur_pos; in tegra_qspi_calculate_curr_xfer_param()
229 unsigned int bits_per_word = t->bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
231 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_qspi_calculate_curr_xfer_param()
241 bits_per_word == 32) && t->len > 3) { in tegra_qspi_calculate_curr_xfer_param()
242 tqspi->is_packed = true; in tegra_qspi_calculate_curr_xfer_param()
243 tqspi->words_per_32bit = 32 / bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
245 tqspi->is_packed = false; in tegra_qspi_calculate_curr_xfer_param()
246 tqspi->words_per_32bit = 1; in tegra_qspi_calculate_curr_xfer_param()
249 if (tqspi->is_packed) { in tegra_qspi_calculate_curr_xfer_param()
250 max_len = min(remain_len, tqspi->max_buf_size); in tegra_qspi_calculate_curr_xfer_param()
251 tqspi->curr_dma_words = max_len / tqspi->bytes_per_word; in tegra_qspi_calculate_curr_xfer_param()
254 max_word = (remain_len - 1) / tqspi->bytes_per_word + 1; in tegra_qspi_calculate_curr_xfer_param()
255 max_word = min(max_word, tqspi->max_buf_size / 4); in tegra_qspi_calculate_curr_xfer_param()
256 tqspi->curr_dma_words = max_word; in tegra_qspi_calculate_curr_xfer_param()
268 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
274 if (tqspi->is_packed) { in tegra_qspi_fill_tx_fifo_from_client_txbuf()
275 fifo_words_left = tx_empty_count * tqspi->words_per_32bit; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
276 written_words = min(fifo_words_left, tqspi->curr_dma_words); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
277 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
282 for (i = 0; (i < 4) && len; i++, len--) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
287 tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
290 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
292 max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
294 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
295 if (len > t->len - tqspi->cur_pos) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
296 len = t->len - tqspi->cur_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
301 for (i = 0; len && (i < bytes_per_word); i++, len--) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
306 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
315 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
322 if (tqspi->is_packed) { in tegra_qspi_read_rx_fifo_to_client_rxbuf()
323 len = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
327 for (i = 0; len && (i < 4); i++, len--) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
331 read_words += tqspi->curr_dma_words; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
332 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
334 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
335 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
339 if (len > t->len - tqspi->cur_pos) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
340 len = t->len - tqspi->cur_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
345 for (i = 0; len && (i < bytes_per_word); i++, len--) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
350 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
359 dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
360 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
370 if (tqspi->is_packed) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
371 tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
373 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
380 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
381 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
382 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
384 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
387 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
389 tqspi->tx_dma_buf[count] = x; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
392 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
395 dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
396 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
402 dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
403 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
405 if (tqspi->is_packed) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
406 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
408 unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
409 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
417 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
418 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
419 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
421 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
422 u32 x = tqspi->rx_dma_buf[count] & rx_mask; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
424 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
428 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
431 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
432 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
446 reinit_completion(&tqspi->tx_dma_complete); in tegra_qspi_start_tx_dma()
448 if (tqspi->is_packed) in tegra_qspi_start_tx_dma()
449 tx_dma_phys = t->tx_dma; in tegra_qspi_start_tx_dma()
451 tx_dma_phys = tqspi->tx_dma_phys; in tegra_qspi_start_tx_dma()
453 tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys, in tegra_qspi_start_tx_dma()
457 if (!tqspi->tx_dma_desc) { in tegra_qspi_start_tx_dma()
458 dev_err(tqspi->dev, "Unable to get TX descriptor\n"); in tegra_qspi_start_tx_dma()
459 return -EIO; in tegra_qspi_start_tx_dma()
462 tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_tx_dma()
463 tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete; in tegra_qspi_start_tx_dma()
464 dmaengine_submit(tqspi->tx_dma_desc); in tegra_qspi_start_tx_dma()
465 dma_async_issue_pending(tqspi->tx_dma_chan); in tegra_qspi_start_tx_dma()
474 reinit_completion(&tqspi->rx_dma_complete); in tegra_qspi_start_rx_dma()
476 if (tqspi->is_packed) in tegra_qspi_start_rx_dma()
477 rx_dma_phys = t->rx_dma; in tegra_qspi_start_rx_dma()
479 rx_dma_phys = tqspi->rx_dma_phys; in tegra_qspi_start_rx_dma()
481 tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys, in tegra_qspi_start_rx_dma()
485 if (!tqspi->rx_dma_desc) { in tegra_qspi_start_rx_dma()
486 dev_err(tqspi->dev, "Unable to get RX descriptor\n"); in tegra_qspi_start_rx_dma()
487 return -EIO; in tegra_qspi_start_rx_dma()
490 tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_rx_dma()
491 tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete; in tegra_qspi_start_rx_dma()
492 dmaengine_submit(tqspi->rx_dma_desc); in tegra_qspi_start_rx_dma()
493 dma_async_issue_pending(tqspi->rx_dma_chan); in tegra_qspi_start_rx_dma()
500 void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS; in tegra_qspi_flush_fifos()
531 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_dma_map_xfer()
532 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_dma_map_xfer()
535 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_map_xfer()
537 if (t->tx_buf) { in tegra_qspi_dma_map_xfer()
538 t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
539 if (dma_mapping_error(tqspi->dev, t->tx_dma)) in tegra_qspi_dma_map_xfer()
540 return -ENOMEM; in tegra_qspi_dma_map_xfer()
543 if (t->rx_buf) { in tegra_qspi_dma_map_xfer()
544 t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE); in tegra_qspi_dma_map_xfer()
545 if (dma_mapping_error(tqspi->dev, t->rx_dma)) { in tegra_qspi_dma_map_xfer()
546 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
547 return -ENOMEM; in tegra_qspi_dma_map_xfer()
558 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_unmap_xfer()
560 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_unmap_xfer()
561 dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); in tegra_qspi_dma_unmap_xfer()
572 if (tqspi->is_packed) { in tegra_qspi_start_dma_based_transfer()
578 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); in tegra_qspi_start_dma_based_transfer()
583 if (tqspi->is_packed) in tegra_qspi_start_dma_based_transfer()
584 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_start_dma_based_transfer()
586 len = tqspi->curr_dma_words * 4; in tegra_qspi_start_dma_based_transfer()
602 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
605 if (tqspi->cur_direction & DATA_DIR_TX) { in tegra_qspi_start_dma_based_transfer()
606 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; in tegra_qspi_start_dma_based_transfer()
609 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
611 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
618 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
623 if (tqspi->cur_direction & DATA_DIR_RX) { in tegra_qspi_start_dma_based_transfer()
624 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; in tegra_qspi_start_dma_based_transfer()
627 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
629 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
633 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_start_dma_based_transfer()
634 tqspi->dma_buf_size, in tegra_qspi_start_dma_based_transfer()
639 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
640 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_dma_based_transfer()
641 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_start_dma_based_transfer()
646 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_start_dma_based_transfer()
648 tqspi->is_curr_dma_xfer = true; in tegra_qspi_start_dma_based_transfer()
649 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
661 if (qspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_cpu_based_transfer()
664 cur_words = qspi->curr_dma_words; in tegra_qspi_start_cpu_based_transfer()
666 val = QSPI_DMA_BLK_SET(cur_words - 1); in tegra_qspi_start_cpu_based_transfer()
671 qspi->is_curr_dma_xfer = false; in tegra_qspi_start_cpu_based_transfer()
672 val = qspi->command1_reg; in tegra_qspi_start_cpu_based_transfer()
681 if (tqspi->tx_dma_buf) { in tegra_qspi_deinit_dma()
682 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
683 tqspi->tx_dma_buf, tqspi->tx_dma_phys); in tegra_qspi_deinit_dma()
684 tqspi->tx_dma_buf = NULL; in tegra_qspi_deinit_dma()
687 if (tqspi->tx_dma_chan) { in tegra_qspi_deinit_dma()
688 dma_release_channel(tqspi->tx_dma_chan); in tegra_qspi_deinit_dma()
689 tqspi->tx_dma_chan = NULL; in tegra_qspi_deinit_dma()
692 if (tqspi->rx_dma_buf) { in tegra_qspi_deinit_dma()
693 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
694 tqspi->rx_dma_buf, tqspi->rx_dma_phys); in tegra_qspi_deinit_dma()
695 tqspi->rx_dma_buf = NULL; in tegra_qspi_deinit_dma()
698 if (tqspi->rx_dma_chan) { in tegra_qspi_deinit_dma()
699 dma_release_channel(tqspi->rx_dma_chan); in tegra_qspi_deinit_dma()
700 tqspi->rx_dma_chan = NULL; in tegra_qspi_deinit_dma()
711 dma_chan = dma_request_chan(tqspi->dev, "rx"); in tegra_qspi_init_dma()
717 tqspi->rx_dma_chan = dma_chan; in tegra_qspi_init_dma()
719 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
721 err = -ENOMEM; in tegra_qspi_init_dma()
725 tqspi->rx_dma_buf = dma_buf; in tegra_qspi_init_dma()
726 tqspi->rx_dma_phys = dma_phys; in tegra_qspi_init_dma()
728 dma_chan = dma_request_chan(tqspi->dev, "tx"); in tegra_qspi_init_dma()
734 tqspi->tx_dma_chan = dma_chan; in tegra_qspi_init_dma()
736 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
738 err = -ENOMEM; in tegra_qspi_init_dma()
742 tqspi->tx_dma_buf = dma_buf; in tegra_qspi_init_dma()
743 tqspi->tx_dma_phys = dma_phys; in tegra_qspi_init_dma()
744 tqspi->use_dma = true; in tegra_qspi_init_dma()
751 if (err != -EPROBE_DEFER) { in tegra_qspi_init_dma()
752 dev_err(tqspi->dev, "cannot use DMA: %d\n", err); in tegra_qspi_init_dma()
753 dev_err(tqspi->dev, "falling back to PIO\n"); in tegra_qspi_init_dma()
763 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup_transfer_one()
764 struct tegra_qspi_client_data *cdata = spi->controller_data; in tegra_qspi_setup_transfer_one()
765 u32 command1, command2, speed = t->speed_hz; in tegra_qspi_setup_transfer_one()
766 u8 bits_per_word = t->bits_per_word; in tegra_qspi_setup_transfer_one()
770 if (speed != tqspi->cur_speed) { in tegra_qspi_setup_transfer_one()
771 clk_set_rate(tqspi->clk, speed); in tegra_qspi_setup_transfer_one()
772 tqspi->cur_speed = speed; in tegra_qspi_setup_transfer_one()
775 tqspi->cur_pos = 0; in tegra_qspi_setup_transfer_one()
776 tqspi->cur_rx_pos = 0; in tegra_qspi_setup_transfer_one()
777 tqspi->cur_tx_pos = 0; in tegra_qspi_setup_transfer_one()
778 tqspi->curr_xfer = t; in tegra_qspi_setup_transfer_one()
783 command1 = tqspi->def_command1_reg; in tegra_qspi_setup_transfer_one()
784 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); in tegra_qspi_setup_transfer_one()
787 req_mode = spi->mode & 0x3; in tegra_qspi_setup_transfer_one()
793 if (spi->mode & SPI_CS_HIGH) in tegra_qspi_setup_transfer_one()
799 if (cdata && cdata->tx_clk_tap_delay) in tegra_qspi_setup_transfer_one()
800 tx_tap = cdata->tx_clk_tap_delay; in tegra_qspi_setup_transfer_one()
802 if (cdata && cdata->rx_clk_tap_delay) in tegra_qspi_setup_transfer_one()
803 rx_tap = cdata->rx_clk_tap_delay; in tegra_qspi_setup_transfer_one()
806 if (command2 != tqspi->def_command2_reg) in tegra_qspi_setup_transfer_one()
810 command1 = tqspi->command1_reg; in tegra_qspi_setup_transfer_one()
812 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); in tegra_qspi_setup_transfer_one()
823 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_start_transfer_one()
831 if (tqspi->is_packed) in tegra_qspi_start_transfer_one()
835 tqspi->cur_direction = 0; in tegra_qspi_start_transfer_one()
838 if (t->rx_buf) { in tegra_qspi_start_transfer_one()
840 tqspi->cur_direction |= DATA_DIR_RX; in tegra_qspi_start_transfer_one()
841 bus_width = t->rx_nbits; in tegra_qspi_start_transfer_one()
844 if (t->tx_buf) { in tegra_qspi_start_transfer_one()
846 tqspi->cur_direction |= DATA_DIR_TX; in tegra_qspi_start_transfer_one()
847 bus_width = t->tx_nbits; in tegra_qspi_start_transfer_one()
859 tqspi->command1_reg = command1; in tegra_qspi_start_transfer_one()
861 tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG); in tegra_qspi_start_transfer_one()
867 if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH) in tegra_qspi_start_transfer_one()
878 struct device_node *slave_np = spi->dev.of_node; in tegra_qspi_parse_cdata_dt()
884 of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay", in tegra_qspi_parse_cdata_dt()
885 &cdata->tx_clk_tap_delay); in tegra_qspi_parse_cdata_dt()
886 of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay", in tegra_qspi_parse_cdata_dt()
887 &cdata->rx_clk_tap_delay); in tegra_qspi_parse_cdata_dt()
893 struct tegra_qspi_client_data *cdata = spi->controller_data; in tegra_qspi_cleanup()
895 spi->controller_data = NULL; in tegra_qspi_cleanup()
901 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup()
902 struct tegra_qspi_client_data *cdata = spi->controller_data; in tegra_qspi_setup()
907 ret = pm_runtime_resume_and_get(tqspi->dev); in tegra_qspi_setup()
909 dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_setup()
915 spi->controller_data = cdata; in tegra_qspi_setup()
918 spin_lock_irqsave(&tqspi->lock, flags); in tegra_qspi_setup()
921 val = tqspi->def_command1_reg; in tegra_qspi_setup()
922 if (spi->mode & SPI_CS_HIGH) in tegra_qspi_setup()
927 tqspi->def_command1_reg = val; in tegra_qspi_setup()
928 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_setup()
930 spin_unlock_irqrestore(&tqspi->lock, flags); in tegra_qspi_setup()
932 pm_runtime_put(tqspi->dev); in tegra_qspi_setup()
939 dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n"); in tegra_qspi_dump_regs()
940 dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_qspi_dump_regs()
943 dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_qspi_dump_regs()
946 dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n", in tegra_qspi_dump_regs()
949 dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_qspi_dump_regs()
956 dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg); in tegra_qspi_handle_error()
959 reset_control_assert(tqspi->rst); in tegra_qspi_handle_error()
961 reset_control_deassert(tqspi->rst); in tegra_qspi_handle_error()
966 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_transfer_end()
967 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; in tegra_qspi_transfer_end()
970 tqspi->command1_reg |= QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
972 tqspi->command1_reg &= ~QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
973 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
974 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
980 struct spi_device *spi = msg->spi; in tegra_qspi_transfer_one_message()
985 msg->status = 0; in tegra_qspi_transfer_one_message()
986 msg->actual_length = 0; in tegra_qspi_transfer_one_message()
987 tqspi->tx_status = 0; in tegra_qspi_transfer_one_message()
988 tqspi->rx_status = 0; in tegra_qspi_transfer_one_message()
990 list_for_each_entry(transfer, &msg->transfers, transfer_list) { in tegra_qspi_transfer_one_message()
995 tqspi->dummy_cycles = 0; in tegra_qspi_transfer_one_message()
1002 if (!list_is_last(&xfer->transfer_list, &msg->transfers)) { in tegra_qspi_transfer_one_message()
1006 if (next_xfer->dummy_data) { in tegra_qspi_transfer_one_message()
1007 u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits; in tegra_qspi_transfer_one_message()
1010 tqspi->dummy_cycles = dummy_cycles; in tegra_qspi_transfer_one_message()
1011 dummy_bytes = next_xfer->len; in tegra_qspi_transfer_one_message()
1017 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_transfer_one_message()
1023 dev_err(tqspi->dev, "failed to start transfer: %d\n", ret); in tegra_qspi_transfer_one_message()
1028 ret = wait_for_completion_timeout(&tqspi->xfer_completion, in tegra_qspi_transfer_one_message()
1031 dev_err(tqspi->dev, "transfer timeout\n"); in tegra_qspi_transfer_one_message()
1032 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_transfer_one_message()
1033 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_transfer_one_message()
1034 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_transfer_one_message()
1035 dmaengine_terminate_all(tqspi->rx_dma_chan); in tegra_qspi_transfer_one_message()
1037 ret = -EIO; in tegra_qspi_transfer_one_message()
1041 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_transfer_one_message()
1043 ret = -EIO; in tegra_qspi_transfer_one_message()
1047 msg->actual_length += xfer->len + dummy_bytes; in tegra_qspi_transfer_one_message()
1056 if (list_is_last(&xfer->transfer_list, &msg->transfers)) { in tegra_qspi_transfer_one_message()
1057 /* de-activate CS after last transfer only when cs_change is not set */ in tegra_qspi_transfer_one_message()
1058 if (!xfer->cs_change) { in tegra_qspi_transfer_one_message()
1062 } else if (xfer->cs_change) { in tegra_qspi_transfer_one_message()
1063 /* de-activated CS between the transfers only when cs_change is set */ in tegra_qspi_transfer_one_message()
1071 msg->status = ret; in tegra_qspi_transfer_one_message()
1078 struct spi_transfer *t = tqspi->curr_xfer; in handle_cpu_based_xfer()
1081 spin_lock_irqsave(&tqspi->lock, flags); in handle_cpu_based_xfer()
1083 if (tqspi->tx_status || tqspi->rx_status) { in handle_cpu_based_xfer()
1085 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1089 if (tqspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1092 if (tqspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1093 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_cpu_based_xfer()
1095 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_cpu_based_xfer()
1097 if (tqspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1098 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1105 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_cpu_based_xfer()
1111 struct spi_transfer *t = tqspi->curr_xfer; in handle_dma_based_xfer()
1117 if (tqspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1118 if (tqspi->tx_status) { in handle_dma_based_xfer()
1119 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1123 &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1125 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1126 dev_err(tqspi->dev, "failed TX DMA transfer\n"); in handle_dma_based_xfer()
1132 if (tqspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1133 if (tqspi->rx_status) { in handle_dma_based_xfer()
1134 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1138 &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1140 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1141 dev_err(tqspi->dev, "failed RX DMA transfer\n"); in handle_dma_based_xfer()
1147 spin_lock_irqsave(&tqspi->lock, flags); in handle_dma_based_xfer()
1152 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1156 if (tqspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1159 if (tqspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1160 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_dma_based_xfer()
1162 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_dma_based_xfer()
1164 if (tqspi->cur_pos == t->len) { in handle_dma_based_xfer()
1166 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1180 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_dma_based_xfer()
1188 tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_isr_thread()
1190 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_isr_thread()
1191 tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF); in tegra_qspi_isr_thread()
1193 if (tqspi->cur_direction & DATA_DIR_RX) in tegra_qspi_isr_thread()
1194 tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF); in tegra_qspi_isr_thread()
1198 if (!tqspi->is_curr_dma_xfer) in tegra_qspi_isr_thread()
1205 { .compatible = "nvidia,tegra210-qspi", },
1206 { .compatible = "nvidia,tegra186-qspi", },
1207 { .compatible = "nvidia,tegra194-qspi", },
1221 master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi)); in tegra_qspi_probe()
1223 return -ENOMEM; in tegra_qspi_probe()
1228 master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | in tegra_qspi_probe()
1230 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); in tegra_qspi_probe()
1231 master->setup = tegra_qspi_setup; in tegra_qspi_probe()
1232 master->cleanup = tegra_qspi_cleanup; in tegra_qspi_probe()
1233 master->transfer_one_message = tegra_qspi_transfer_one_message; in tegra_qspi_probe()
1234 master->num_chipselect = 1; in tegra_qspi_probe()
1235 master->auto_runtime_pm = true; in tegra_qspi_probe()
1237 bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); in tegra_qspi_probe()
1239 master->bus_num = bus_num; in tegra_qspi_probe()
1241 tqspi->master = master; in tegra_qspi_probe()
1242 tqspi->dev = &pdev->dev; in tegra_qspi_probe()
1243 spin_lock_init(&tqspi->lock); in tegra_qspi_probe()
1246 tqspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_qspi_probe()
1247 if (IS_ERR(tqspi->base)) in tegra_qspi_probe()
1248 return PTR_ERR(tqspi->base); in tegra_qspi_probe()
1250 tqspi->phys = r->start; in tegra_qspi_probe()
1252 tqspi->irq = qspi_irq; in tegra_qspi_probe()
1254 tqspi->clk = devm_clk_get(&pdev->dev, "qspi"); in tegra_qspi_probe()
1255 if (IS_ERR(tqspi->clk)) { in tegra_qspi_probe()
1256 ret = PTR_ERR(tqspi->clk); in tegra_qspi_probe()
1257 dev_err(&pdev->dev, "failed to get clock: %d\n", ret); in tegra_qspi_probe()
1261 tqspi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in tegra_qspi_probe()
1262 if (IS_ERR(tqspi->rst)) { in tegra_qspi_probe()
1263 ret = PTR_ERR(tqspi->rst); in tegra_qspi_probe()
1264 dev_err(&pdev->dev, "failed to get reset control: %d\n", ret); in tegra_qspi_probe()
1268 tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2; in tegra_qspi_probe()
1269 tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN; in tegra_qspi_probe()
1275 if (tqspi->use_dma) in tegra_qspi_probe()
1276 tqspi->max_buf_size = tqspi->dma_buf_size; in tegra_qspi_probe()
1278 init_completion(&tqspi->tx_dma_complete); in tegra_qspi_probe()
1279 init_completion(&tqspi->rx_dma_complete); in tegra_qspi_probe()
1280 init_completion(&tqspi->xfer_completion); in tegra_qspi_probe()
1282 pm_runtime_enable(&pdev->dev); in tegra_qspi_probe()
1283 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_qspi_probe()
1285 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_probe()
1289 reset_control_assert(tqspi->rst); in tegra_qspi_probe()
1291 reset_control_deassert(tqspi->rst); in tegra_qspi_probe()
1293 tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL; in tegra_qspi_probe()
1294 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_probe()
1295 tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1); in tegra_qspi_probe()
1296 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2); in tegra_qspi_probe()
1297 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2); in tegra_qspi_probe()
1299 pm_runtime_put(&pdev->dev); in tegra_qspi_probe()
1301 ret = request_threaded_irq(tqspi->irq, NULL, in tegra_qspi_probe()
1303 dev_name(&pdev->dev), tqspi); in tegra_qspi_probe()
1305 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret); in tegra_qspi_probe()
1309 master->dev.of_node = pdev->dev.of_node; in tegra_qspi_probe()
1312 dev_err(&pdev->dev, "failed to register master: %d\n", ret); in tegra_qspi_probe()
1321 pm_runtime_disable(&pdev->dev); in tegra_qspi_probe()
1332 free_irq(tqspi->irq, tqspi); in tegra_qspi_remove()
1333 pm_runtime_disable(&pdev->dev); in tegra_qspi_remove()
1358 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_resume()
1359 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2); in tegra_qspi_resume()
1373 clk_disable_unprepare(tqspi->clk); in tegra_qspi_runtime_suspend()
1384 ret = clk_prepare_enable(tqspi->clk); in tegra_qspi_runtime_resume()
1386 dev_err(tqspi->dev, "failed to enable clock: %d\n", ret); in tegra_qspi_runtime_resume()
1398 .name = "tegra-qspi",
1407 MODULE_ALIAS("platform:qspi-tegra");