Lines Matching +full:clock +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/dma-mapping.h>
21 #include <linux/platform_data/spi-s3c64xx.h>
28 /* Registers and bit-fields */
106 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
110 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
119 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
131 * struct s3c64xx_spi_port_config - SPI Controller hardware info
132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
137 * @clk_from_cmu: True, if the controller does not include a clock mux and
139 * @clk_ioclk: True if clock is present on this device
142 * differ in some aspects such as the size of the fifo and spi bus clock
157 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
158 * @clk: Pointer to the spi clock.
159 * @src_clk: Pointer to the clock used to generate SPI signals.
160 * @ioclk: Pointer to the i/o clock between master and slave
162 * @master: Pointer to the SPI Protocol master.
171 * @cur_speed: Current clock speed
183 struct spi_master *master; member
199 void __iomem *regs = sdd->regs; in s3c64xx_flush_fifo()
218 } while (TX_FIFO_LVL(val, sdd) && loops--); in s3c64xx_flush_fifo()
221 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); in s3c64xx_flush_fifo()
231 } while (loops--); in s3c64xx_flush_fifo()
234 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); in s3c64xx_flush_fifo()
251 if (dma->direction == DMA_DEV_TO_MEM) in s3c64xx_spi_dmacb()
258 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_dmacb()
260 if (dma->direction == DMA_DEV_TO_MEM) { in s3c64xx_spi_dmacb()
261 sdd->state &= ~RXBUSY; in s3c64xx_spi_dmacb()
262 if (!(sdd->state & TXBUSY)) in s3c64xx_spi_dmacb()
263 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
265 sdd->state &= ~TXBUSY; in s3c64xx_spi_dmacb()
266 if (!(sdd->state & RXBUSY)) in s3c64xx_spi_dmacb()
267 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
270 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_dmacb()
283 if (dma->direction == DMA_DEV_TO_MEM) { in prepare_dma()
286 config.direction = dma->direction; in prepare_dma()
287 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; in prepare_dma()
288 config.src_addr_width = sdd->cur_bpw / 8; in prepare_dma()
290 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
294 config.direction = dma->direction; in prepare_dma()
295 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; in prepare_dma()
296 config.dst_addr_width = sdd->cur_bpw / 8; in prepare_dma()
298 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
301 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, in prepare_dma()
302 dma->direction, DMA_PREP_INTERRUPT); in prepare_dma()
304 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", in prepare_dma()
305 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); in prepare_dma()
306 return -ENOMEM; in prepare_dma()
309 desc->callback = s3c64xx_spi_dmacb; in prepare_dma()
310 desc->callback_param = dma; in prepare_dma()
312 dma->cookie = dmaengine_submit(desc); in prepare_dma()
313 ret = dma_submit_error(dma->cookie); in prepare_dma()
315 dev_err(&sdd->pdev->dev, "DMA submission failed"); in prepare_dma()
316 return -EIO; in prepare_dma()
319 dma_async_issue_pending(dma->ch); in prepare_dma()
326 spi_master_get_devdata(spi->master); in s3c64xx_spi_set_cs()
328 if (sdd->cntrlr_info->no_cs) in s3c64xx_spi_set_cs()
332 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { in s3c64xx_spi_set_cs()
333 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
335 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
339 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
342 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_set_cs()
344 sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
355 spi->dma_rx = sdd->rx_dma.ch; in s3c64xx_spi_prepare_transfer()
356 spi->dma_tx = sdd->tx_dma.ch; in s3c64xx_spi_prepare_transfer()
361 static bool s3c64xx_spi_can_dma(struct spi_master *master, in s3c64xx_spi_can_dma() argument
365 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_can_dma()
367 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; in s3c64xx_spi_can_dma()
373 void __iomem *regs = sdd->regs; in s3c64xx_enable_datapath()
391 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
396 if (xfer->tx_buf != NULL) { in s3c64xx_enable_datapath()
397 sdd->state |= TXBUSY; in s3c64xx_enable_datapath()
401 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); in s3c64xx_enable_datapath()
403 switch (sdd->cur_bpw) { in s3c64xx_enable_datapath()
406 xfer->tx_buf, xfer->len / 4); in s3c64xx_enable_datapath()
410 xfer->tx_buf, xfer->len / 2); in s3c64xx_enable_datapath()
414 xfer->tx_buf, xfer->len); in s3c64xx_enable_datapath()
420 if (xfer->rx_buf != NULL) { in s3c64xx_enable_datapath()
421 sdd->state |= RXBUSY; in s3c64xx_enable_datapath()
423 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL in s3c64xx_enable_datapath()
424 && !(sdd->cur_mode & SPI_CPHA)) in s3c64xx_enable_datapath()
430 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
433 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); in s3c64xx_enable_datapath()
449 void __iomem *regs = sdd->regs; in s3c64xx_spi_wait_for_timeout()
461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); in s3c64xx_spi_wait_for_timeout()
470 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_dma()
476 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_dma()
481 val = wait_for_completion_timeout(&sdd->xfer_completion, val); in s3c64xx_wait_for_dma()
485 * proceed further else return -EIO. in s3c64xx_wait_for_dma()
492 if (val && !xfer->rx_buf) { in s3c64xx_wait_for_dma()
497 && --val) { in s3c64xx_wait_for_dma()
506 return -EIO; in s3c64xx_wait_for_dma()
514 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_pio()
523 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_pio()
529 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); in s3c64xx_wait_for_pio()
532 return -EIO; in s3c64xx_wait_for_pio()
535 if (!xfer->rx_buf) { in s3c64xx_wait_for_pio()
536 sdd->state &= ~TXBUSY; in s3c64xx_wait_for_pio()
548 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); in s3c64xx_wait_for_pio()
549 buf = xfer->rx_buf; in s3c64xx_wait_for_pio()
555 switch (sdd->cur_bpw) { in s3c64xx_wait_for_pio()
571 } while (loops--); in s3c64xx_wait_for_pio()
572 sdd->state &= ~RXBUSY; in s3c64xx_wait_for_pio()
579 void __iomem *regs = sdd->regs; in s3c64xx_spi_config()
583 /* Disable Clock */ in s3c64xx_spi_config()
584 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
596 if (sdd->cur_mode & SPI_CPOL) in s3c64xx_spi_config()
599 if (sdd->cur_mode & SPI_CPHA) in s3c64xx_spi_config()
609 switch (sdd->cur_bpw) { in s3c64xx_spi_config()
626 if (sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
627 /* The src_clk clock is divided internally by 2 */ in s3c64xx_spi_config()
628 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); in s3c64xx_spi_config()
631 sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; in s3c64xx_spi_config()
633 /* Configure Clock */ in s3c64xx_spi_config()
636 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) in s3c64xx_spi_config()
640 /* Enable Clock */ in s3c64xx_spi_config()
651 static int s3c64xx_spi_prepare_message(struct spi_master *master, in s3c64xx_spi_prepare_message() argument
654 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_prepare_message()
655 struct spi_device *spi = msg->spi; in s3c64xx_spi_prepare_message()
656 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_prepare_message()
659 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
664 static int s3c64xx_spi_transfer_one(struct spi_master *master, in s3c64xx_spi_transfer_one() argument
668 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_transfer_one()
679 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
682 bpw = xfer->bits_per_word; in s3c64xx_spi_transfer_one()
683 speed = xfer->speed_hz; in s3c64xx_spi_transfer_one()
685 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { in s3c64xx_spi_transfer_one()
686 sdd->cur_bpw = bpw; in s3c64xx_spi_transfer_one()
687 sdd->cur_speed = speed; in s3c64xx_spi_transfer_one()
688 sdd->cur_mode = spi->mode; in s3c64xx_spi_transfer_one()
694 if (!is_polling(sdd) && (xfer->len > fifo_len) && in s3c64xx_spi_transfer_one()
695 sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_transfer_one()
698 } else if (is_polling(sdd) && xfer->len > fifo_len) { in s3c64xx_spi_transfer_one()
699 tx_buf = xfer->tx_buf; in s3c64xx_spi_transfer_one()
700 rx_buf = xfer->rx_buf; in s3c64xx_spi_transfer_one()
701 origin_len = xfer->len; in s3c64xx_spi_transfer_one()
703 target_len = xfer->len; in s3c64xx_spi_transfer_one()
704 if (xfer->len > fifo_len) in s3c64xx_spi_transfer_one()
705 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
709 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
712 sdd->state &= ~RXBUSY; in s3c64xx_spi_transfer_one()
713 sdd->state &= ~TXBUSY; in s3c64xx_spi_transfer_one()
720 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
723 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); in s3c64xx_spi_transfer_one()
733 dev_err(&spi->dev, in s3c64xx_spi_transfer_one()
734 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", in s3c64xx_spi_transfer_one()
735 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, in s3c64xx_spi_transfer_one()
736 (sdd->state & RXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
737 (sdd->state & TXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
738 xfer->len, use_dma ? 1 : 0, status); in s3c64xx_spi_transfer_one()
743 if (xfer->tx_buf && (sdd->state & TXBUSY)) { in s3c64xx_spi_transfer_one()
744 dmaengine_pause(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
745 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
746 dmaengine_terminate_all(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
747 dev_err(&spi->dev, "TX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
750 if (xfer->rx_buf && (sdd->state & RXBUSY)) { in s3c64xx_spi_transfer_one()
751 dmaengine_pause(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
752 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
753 dmaengine_terminate_all(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
754 dev_err(&spi->dev, "RX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
761 target_len -= xfer->len; in s3c64xx_spi_transfer_one()
763 if (xfer->tx_buf) in s3c64xx_spi_transfer_one()
764 xfer->tx_buf += xfer->len; in s3c64xx_spi_transfer_one()
766 if (xfer->rx_buf) in s3c64xx_spi_transfer_one()
767 xfer->rx_buf += xfer->len; in s3c64xx_spi_transfer_one()
770 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
772 xfer->len = target_len; in s3c64xx_spi_transfer_one()
778 xfer->tx_buf = tx_buf; in s3c64xx_spi_transfer_one()
779 xfer->rx_buf = rx_buf; in s3c64xx_spi_transfer_one()
780 xfer->len = origin_len; in s3c64xx_spi_transfer_one()
793 slave_np = spi->dev.of_node; in s3c64xx_get_slave_ctrldata()
795 dev_err(&spi->dev, "device node not found\n"); in s3c64xx_get_slave_ctrldata()
796 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
799 data_np = of_get_child_by_name(slave_np, "controller-data"); in s3c64xx_get_slave_ctrldata()
801 dev_err(&spi->dev, "child node 'controller-data' not found\n"); in s3c64xx_get_slave_ctrldata()
802 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
808 return ERR_PTR(-ENOMEM); in s3c64xx_get_slave_ctrldata()
811 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); in s3c64xx_get_slave_ctrldata()
812 cs->fb_delay = fb_delay; in s3c64xx_get_slave_ctrldata()
819 * and save the configuration in a local data-structure.
825 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_setup()
829 sdd = spi_master_get_devdata(spi->master); in s3c64xx_spi_setup()
830 if (spi->dev.of_node) { in s3c64xx_spi_setup()
832 spi->controller_data = cs; in s3c64xx_spi_setup()
834 /* On non-DT platforms the SPI core will set spi->cs_gpio in s3c64xx_spi_setup()
835 * to -ENOENT. The GPIO pin used to drive the chip select in s3c64xx_spi_setup()
836 * is defined by using platform data so spi->cs_gpio value in s3c64xx_spi_setup()
839 spi->cs_gpio = cs->line; in s3c64xx_spi_setup()
843 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); in s3c64xx_spi_setup()
844 return -ENODEV; in s3c64xx_spi_setup()
848 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_setup()
849 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, in s3c64xx_spi_setup()
850 dev_name(&spi->dev)); in s3c64xx_spi_setup()
852 dev_err(&spi->dev, in s3c64xx_spi_setup()
854 spi->cs_gpio, err); in s3c64xx_spi_setup()
862 pm_runtime_get_sync(&sdd->pdev->dev); in s3c64xx_spi_setup()
865 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_setup()
869 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); in s3c64xx_spi_setup()
871 if (spi->max_speed_hz > speed) in s3c64xx_spi_setup()
872 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
874 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
877 psr--; in s3c64xx_spi_setup()
879 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
880 if (spi->max_speed_hz < speed) { in s3c64xx_spi_setup()
884 err = -EINVAL; in s3c64xx_spi_setup()
889 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
890 if (spi->max_speed_hz >= speed) { in s3c64xx_spi_setup()
891 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
893 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", in s3c64xx_spi_setup()
894 spi->max_speed_hz); in s3c64xx_spi_setup()
895 err = -EINVAL; in s3c64xx_spi_setup()
900 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
901 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
907 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
908 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
909 /* setup() returns with device de-selected */ in s3c64xx_spi_setup()
912 if (gpio_is_valid(spi->cs_gpio)) in s3c64xx_spi_setup()
913 gpio_free(spi->cs_gpio); in s3c64xx_spi_setup()
917 if (spi->dev.of_node) in s3c64xx_spi_setup()
927 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_cleanup()
928 gpio_free(spi->cs_gpio); in s3c64xx_spi_cleanup()
929 if (spi->dev.of_node) in s3c64xx_spi_cleanup()
932 /* On non-DT platforms, the SPI core sets in s3c64xx_spi_cleanup()
933 * spi->cs_gpio to -ENOENT and .setup() in s3c64xx_spi_cleanup()
937 spi->cs_gpio = -ENOENT; in s3c64xx_spi_cleanup()
947 struct spi_master *spi = sdd->master; in s3c64xx_spi_irq()
950 val = readl(sdd->regs + S3C64XX_SPI_STATUS); in s3c64xx_spi_irq()
954 dev_err(&spi->dev, "RX overrun\n"); in s3c64xx_spi_irq()
958 dev_err(&spi->dev, "RX underrun\n"); in s3c64xx_spi_irq()
962 dev_err(&spi->dev, "TX overrun\n"); in s3c64xx_spi_irq()
966 dev_err(&spi->dev, "TX underrun\n"); in s3c64xx_spi_irq()
970 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
971 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
978 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_hwinit()
979 void __iomem *regs = sdd->regs; in s3c64xx_spi_hwinit()
982 sdd->cur_speed = 0; in s3c64xx_spi_hwinit()
984 if (sci->no_cs) in s3c64xx_spi_hwinit()
985 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
986 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_hwinit()
987 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
989 /* Disable Interrupts - we use Polling if not DMA mode */ in s3c64xx_spi_hwinit()
992 if (!sdd->port_conf->clk_from_cmu) in s3c64xx_spi_hwinit()
993 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, in s3c64xx_spi_hwinit()
1025 return ERR_PTR(-ENOMEM); in s3c64xx_spi_parse_dt()
1027 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { in s3c64xx_spi_parse_dt()
1028 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); in s3c64xx_spi_parse_dt()
1029 sci->src_clk_nr = 0; in s3c64xx_spi_parse_dt()
1031 sci->src_clk_nr = temp; in s3c64xx_spi_parse_dt()
1034 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { in s3c64xx_spi_parse_dt()
1036 sci->num_cs = 1; in s3c64xx_spi_parse_dt()
1038 sci->num_cs = temp; in s3c64xx_spi_parse_dt()
1041 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); in s3c64xx_spi_parse_dt()
1056 if (pdev->dev.of_node) in s3c64xx_spi_get_port_config()
1057 return of_device_get_match_data(&pdev->dev); in s3c64xx_spi_get_port_config()
1059 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; in s3c64xx_spi_get_port_config()
1066 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); in s3c64xx_spi_probe()
1067 struct spi_master *master; in s3c64xx_spi_probe() local
1071 if (!sci && pdev->dev.of_node) { in s3c64xx_spi_probe()
1072 sci = s3c64xx_spi_parse_dt(&pdev->dev); in s3c64xx_spi_probe()
1078 dev_err(&pdev->dev, "platform_data missing!\n"); in s3c64xx_spi_probe()
1079 return -ENODEV; in s3c64xx_spi_probe()
1084 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); in s3c64xx_spi_probe()
1085 return -ENXIO; in s3c64xx_spi_probe()
1090 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); in s3c64xx_spi_probe()
1094 master = spi_alloc_master(&pdev->dev, in s3c64xx_spi_probe()
1096 if (master == NULL) { in s3c64xx_spi_probe()
1097 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in s3c64xx_spi_probe()
1098 return -ENOMEM; in s3c64xx_spi_probe()
1101 platform_set_drvdata(pdev, master); in s3c64xx_spi_probe()
1103 sdd = spi_master_get_devdata(master); in s3c64xx_spi_probe()
1104 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); in s3c64xx_spi_probe()
1105 sdd->master = master; in s3c64xx_spi_probe()
1106 sdd->cntrlr_info = sci; in s3c64xx_spi_probe()
1107 sdd->pdev = pdev; in s3c64xx_spi_probe()
1108 sdd->sfr_start = mem_res->start; in s3c64xx_spi_probe()
1109 if (pdev->dev.of_node) { in s3c64xx_spi_probe()
1110 ret = of_alias_get_id(pdev->dev.of_node, "spi"); in s3c64xx_spi_probe()
1112 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", in s3c64xx_spi_probe()
1116 sdd->port_id = ret; in s3c64xx_spi_probe()
1118 sdd->port_id = pdev->id; in s3c64xx_spi_probe()
1121 sdd->cur_bpw = 8; in s3c64xx_spi_probe()
1123 sdd->tx_dma.direction = DMA_MEM_TO_DEV; in s3c64xx_spi_probe()
1124 sdd->rx_dma.direction = DMA_DEV_TO_MEM; in s3c64xx_spi_probe()
1126 master->dev.of_node = pdev->dev.of_node; in s3c64xx_spi_probe()
1127 master->bus_num = sdd->port_id; in s3c64xx_spi_probe()
1128 master->setup = s3c64xx_spi_setup; in s3c64xx_spi_probe()
1129 master->cleanup = s3c64xx_spi_cleanup; in s3c64xx_spi_probe()
1130 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; in s3c64xx_spi_probe()
1131 master->prepare_message = s3c64xx_spi_prepare_message; in s3c64xx_spi_probe()
1132 master->transfer_one = s3c64xx_spi_transfer_one; in s3c64xx_spi_probe()
1133 master->num_chipselect = sci->num_cs; in s3c64xx_spi_probe()
1134 master->dma_alignment = 8; in s3c64xx_spi_probe()
1135 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | in s3c64xx_spi_probe()
1137 /* the spi->mode bits understood by this driver: */ in s3c64xx_spi_probe()
1138 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in s3c64xx_spi_probe()
1139 master->auto_runtime_pm = true; in s3c64xx_spi_probe()
1141 master->can_dma = s3c64xx_spi_can_dma; in s3c64xx_spi_probe()
1143 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); in s3c64xx_spi_probe()
1144 if (IS_ERR(sdd->regs)) { in s3c64xx_spi_probe()
1145 ret = PTR_ERR(sdd->regs); in s3c64xx_spi_probe()
1149 if (sci->cfg_gpio && sci->cfg_gpio()) { in s3c64xx_spi_probe()
1150 dev_err(&pdev->dev, "Unable to config gpio\n"); in s3c64xx_spi_probe()
1151 ret = -EBUSY; in s3c64xx_spi_probe()
1156 sdd->clk = devm_clk_get(&pdev->dev, "spi"); in s3c64xx_spi_probe()
1157 if (IS_ERR(sdd->clk)) { in s3c64xx_spi_probe()
1158 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); in s3c64xx_spi_probe()
1159 ret = PTR_ERR(sdd->clk); in s3c64xx_spi_probe()
1163 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_probe()
1165 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); in s3c64xx_spi_probe()
1169 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); in s3c64xx_spi_probe()
1170 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); in s3c64xx_spi_probe()
1171 if (IS_ERR(sdd->src_clk)) { in s3c64xx_spi_probe()
1172 dev_err(&pdev->dev, in s3c64xx_spi_probe()
1173 "Unable to acquire clock '%s'\n", clk_name); in s3c64xx_spi_probe()
1174 ret = PTR_ERR(sdd->src_clk); in s3c64xx_spi_probe()
1178 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_probe()
1180 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); in s3c64xx_spi_probe()
1184 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_probe()
1185 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); in s3c64xx_spi_probe()
1186 if (IS_ERR(sdd->ioclk)) { in s3c64xx_spi_probe()
1187 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); in s3c64xx_spi_probe()
1188 ret = PTR_ERR(sdd->ioclk); in s3c64xx_spi_probe()
1192 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_probe()
1194 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); in s3c64xx_spi_probe()
1201 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx"); in s3c64xx_spi_probe()
1202 if (IS_ERR(sdd->rx_dma.ch)) { in s3c64xx_spi_probe()
1203 dev_err(&pdev->dev, "Failed to get RX DMA channel\n"); in s3c64xx_spi_probe()
1204 ret = PTR_ERR(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1207 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx"); in s3c64xx_spi_probe()
1208 if (IS_ERR(sdd->tx_dma.ch)) { in s3c64xx_spi_probe()
1209 dev_err(&pdev->dev, "Failed to get TX DMA channel\n"); in s3c64xx_spi_probe()
1210 ret = PTR_ERR(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1215 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); in s3c64xx_spi_probe()
1216 pm_runtime_use_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1217 pm_runtime_set_active(&pdev->dev); in s3c64xx_spi_probe()
1218 pm_runtime_enable(&pdev->dev); in s3c64xx_spi_probe()
1219 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_probe()
1224 spin_lock_init(&sdd->lock); in s3c64xx_spi_probe()
1225 init_completion(&sdd->xfer_completion); in s3c64xx_spi_probe()
1227 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, in s3c64xx_spi_probe()
1228 "spi-s3c64xx", sdd); in s3c64xx_spi_probe()
1230 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", in s3c64xx_spi_probe()
1237 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_probe()
1239 ret = devm_spi_register_master(&pdev->dev, master); in s3c64xx_spi_probe()
1241 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); in s3c64xx_spi_probe()
1245 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", in s3c64xx_spi_probe()
1246 sdd->port_id, master->num_chipselect); in s3c64xx_spi_probe()
1247 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", in s3c64xx_spi_probe()
1250 pm_runtime_mark_last_busy(&pdev->dev); in s3c64xx_spi_probe()
1251 pm_runtime_put_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1256 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_probe()
1257 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_probe()
1258 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_probe()
1261 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1264 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1266 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_probe()
1268 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_probe()
1270 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_probe()
1272 spi_master_put(master); in s3c64xx_spi_probe()
1279 struct spi_master *master = platform_get_drvdata(pdev); in s3c64xx_spi_remove() local
1280 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_remove()
1282 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_remove()
1284 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_remove()
1287 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_remove()
1288 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_remove()
1291 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_remove()
1293 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_remove()
1295 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_remove()
1297 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_remove()
1298 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_remove()
1299 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_remove()
1307 struct spi_master *master = dev_get_drvdata(dev); in s3c64xx_spi_suspend() local
1308 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_suspend()
1310 int ret = spi_master_suspend(master); in s3c64xx_spi_suspend()
1318 sdd->cur_speed = 0; /* Output Clock is stopped */ in s3c64xx_spi_suspend()
1325 struct spi_master *master = dev_get_drvdata(dev); in s3c64xx_spi_resume() local
1326 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_resume()
1327 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_resume()
1330 if (sci->cfg_gpio) in s3c64xx_spi_resume()
1331 sci->cfg_gpio(); in s3c64xx_spi_resume()
1337 return spi_master_resume(master); in s3c64xx_spi_resume()
1344 struct spi_master *master = dev_get_drvdata(dev); in s3c64xx_spi_runtime_suspend() local
1345 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_runtime_suspend()
1347 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_runtime_suspend()
1348 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1349 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_suspend()
1356 struct spi_master *master = dev_get_drvdata(dev); in s3c64xx_spi_runtime_resume() local
1357 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); in s3c64xx_spi_runtime_resume()
1360 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_runtime_resume()
1361 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1366 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1370 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_runtime_resume()
1378 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_runtime_resume()
1383 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1385 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1447 .name = "s3c2443-spi",
1450 .name = "s3c6410-spi",
1457 { .compatible = "samsung,s3c2443-spi",
1460 { .compatible = "samsung,s3c6410-spi",
1463 { .compatible = "samsung,s5pv210-spi",
1466 { .compatible = "samsung,exynos4210-spi",
1469 { .compatible = "samsung,exynos7-spi",
1472 { .compatible = "samsung,exynos5433-spi",
1481 .name = "s3c64xx-spi",
1489 MODULE_ALIAS("platform:s3c64xx-spi");