Lines Matching +full:rx +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #include "spi-pxa2xx.h"
38 MODULE_ALIAS("platform:pxa2xx-spi");
80 /* LPSS offset from drv_data->ioaddr */
82 /* Register offsets from drv_data->lpss_base or -1 */
106 .reg_capabilities = -1,
116 .reg_capabilities = -1,
126 .reg_capabilities = -1,
136 .reg_general = -1,
139 .reg_capabilities = -1,
146 .reg_general = -1,
159 .reg_general = -1,
175 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; in lpss_get_config()
180 switch (drv_data->ssp_type) { in is_lpss_ssp()
195 return drv_data->ssp_type == QUARK_X1000_SSP; in is_quark_x1000_ssp()
200 return drv_data->ssp_type == MMP2_SSP; in is_mmp2_ssp()
205 return drv_data->ssp_type == MRFLD_SSP; in is_mrfld_ssp()
216 switch (drv_data->ssp_type) { in pxa2xx_spi_get_ssrc1_change_mask()
229 switch (drv_data->ssp_type) { in pxa2xx_spi_get_rx_default_thre()
243 switch (drv_data->ssp_type) { in pxa2xx_spi_txfifo_full()
263 switch (drv_data->ssp_type) { in pxa2xx_spi_clear_rx_thre()
278 u32 *sccr1_reg, u32 threshold) in pxa2xx_spi_set_rx_thre() argument
280 switch (drv_data->ssp_type) { in pxa2xx_spi_set_rx_thre()
282 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
285 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
288 *sccr1_reg |= SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
296 switch (drv_data->ssp_type) { in pxa2xx_configure_sscr0()
304 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) in pxa2xx_configure_sscr0()
315 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_read_priv()
316 return readl(drv_data->lpss_base + offset); in __lpss_ssp_read_priv()
322 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_write_priv()
323 writel(value, drv_data->lpss_base + offset); in __lpss_ssp_write_priv()
327 * lpss_ssp_setup - perform LPSS SSP specific setup
339 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; in lpss_ssp_setup()
342 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_setup()
345 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_setup()
348 if (drv_data->controller_info->enable_dma) { in lpss_ssp_setup()
349 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); in lpss_ssp_setup()
351 if (config->reg_general >= 0) { in lpss_ssp_setup()
353 config->reg_general); in lpss_ssp_setup()
356 config->reg_general, value); in lpss_ssp_setup()
365 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
368 if (!config->cs_sel_mask) in lpss_ssp_select_cs()
371 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_select_cs()
373 cs = spi->chip_select; in lpss_ssp_select_cs()
374 cs <<= config->cs_sel_shift; in lpss_ssp_select_cs()
375 if (cs != (value & config->cs_sel_mask)) { in lpss_ssp_select_cs()
383 value &= ~config->cs_sel_mask; in lpss_ssp_select_cs()
386 config->reg_cs_ctrl, value); in lpss_ssp_select_cs()
388 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
395 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
404 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_cs_control()
409 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_cs_control()
410 if (config->cs_clk_stays_gated) { in lpss_ssp_cs_control()
432 spi_controller_get_devdata(spi->controller); in cs_assert()
434 if (drv_data->ssp_type == CE4100_SSP) { in cs_assert()
435 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select); in cs_assert()
439 if (chip->cs_control) { in cs_assert()
440 chip->cs_control(PXA2XX_CS_ASSERT); in cs_assert()
452 spi_controller_get_devdata(spi->controller); in cs_deassert()
455 if (drv_data->ssp_type == CE4100_SSP) in cs_deassert()
464 if (chip->cs_control) { in cs_deassert()
465 chip->cs_control(PXA2XX_CS_DEASSERT); in cs_deassert()
488 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
496 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */ in pxa2xx_spi_off()
500 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_off()
505 u8 n_bytes = drv_data->n_bytes; in null_writer()
508 || (drv_data->tx == drv_data->tx_end)) in null_writer()
512 drv_data->tx += n_bytes; in null_writer()
519 u8 n_bytes = drv_data->n_bytes; in null_reader()
521 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in null_reader()
523 drv_data->rx += n_bytes; in null_reader()
526 return drv_data->rx == drv_data->rx_end; in null_reader()
532 || (drv_data->tx == drv_data->tx_end)) in u8_writer()
535 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); in u8_writer()
536 ++drv_data->tx; in u8_writer()
543 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u8_reader()
544 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
545 ++drv_data->rx; in u8_reader()
548 return drv_data->rx == drv_data->rx_end; in u8_reader()
554 || (drv_data->tx == drv_data->tx_end)) in u16_writer()
557 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); in u16_writer()
558 drv_data->tx += 2; in u16_writer()
565 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u16_reader()
566 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
567 drv_data->rx += 2; in u16_reader()
570 return drv_data->rx == drv_data->rx_end; in u16_reader()
576 || (drv_data->tx == drv_data->tx_end)) in u32_writer()
579 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); in u32_writer()
580 drv_data->tx += 4; in u32_writer()
587 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u32_reader()
588 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
589 drv_data->rx += 4; in u32_reader()
592 return drv_data->rx == drv_data->rx_end; in u32_reader()
597 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; in reset_sccr1() local
600 if (drv_data->controller->cur_msg) { in reset_sccr1()
601 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
602 threshold = chip->threshold; in reset_sccr1()
604 threshold = 0; in reset_sccr1()
607 switch (drv_data->ssp_type) { in reset_sccr1()
619 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); in reset_sccr1()
625 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_stop_and_reset()
639 dev_err(drv_data->ssp->dev, "%s\n", msg); in int_error_stop()
641 drv_data->controller->cur_msg->status = err; in int_error_stop()
642 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
649 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
656 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); in interrupt_transfer()
661 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); in interrupt_transfer()
666 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); in interrupt_transfer()
672 if (drv_data->read(drv_data)) { in interrupt_transfer()
678 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ in interrupt_transfer()
680 if (drv_data->read(drv_data)) { in interrupt_transfer()
684 } while (drv_data->write(drv_data)); in interrupt_transfer()
686 if (drv_data->read(drv_data)) { in interrupt_transfer()
691 if (drv_data->tx == drv_data->tx_end) { in interrupt_transfer()
699 * PXA25x_SSP has no timeout, set up Rx threshold for in interrupt_transfer()
700 * the remaining Rx bytes. in interrupt_transfer()
707 bytes_left = drv_data->rx_end - drv_data->rx; in interrupt_transfer()
708 switch (drv_data->n_bytes) { in interrupt_transfer()
735 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); in handle_bad_msg()
742 u32 mask = drv_data->mask_sr; in ssp_int()
751 if (pm_runtime_suspended(drv_data->ssp->dev)) in ssp_int()
770 /* Ignore RX timeout interrupt if it is disabled */ in ssp_int()
777 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); in ssp_int()
780 if (!drv_data->controller->cur_msg) { in ssp_int()
786 return drv_data->transfer_handler(drv_data); in ssp_int()
845 scale = fls_long(q1 - 1); in quark_x1000_get_clk_div()
847 q1 >>= scale - 9; in quark_x1000_get_clk_div()
848 mul >>= scale - 9; in quark_x1000_get_clk_div()
861 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
866 r2 = abs(fref2 / q2 - rate); in quark_x1000_get_clk_div()
896 r1 = abs(fssp - rate); in quark_x1000_get_clk_div()
907 return q - 1; in quark_x1000_get_clk_div()
912 unsigned long ssp_clk = drv_data->controller->max_speed_hz; in ssp_get_clk_div()
913 const struct ssp_device *ssp = drv_data->ssp; in ssp_get_clk_div()
921 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) in ssp_get_clk_div()
922 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; in ssp_get_clk_div()
924 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; in ssp_get_clk_div()
931 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_ssp_get_clk_div()
934 switch (drv_data->ssp_type) { in pxa2xx_ssp_get_clk_div()
936 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
951 return chip->enable_dma && in pxa2xx_spi_can_dma()
952 xfer->len <= MAX_DMA_LEN && in pxa2xx_spi_can_dma()
953 xfer->len >= chip->dma_burst_size; in pxa2xx_spi_can_dma()
961 struct spi_message *message = controller->cur_msg; in pxa2xx_spi_transfer_one()
963 u32 dma_thresh = chip->dma_threshold; in pxa2xx_spi_transfer_one()
964 u32 dma_burst = chip->dma_burst_size; in pxa2xx_spi_transfer_one()
975 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { in pxa2xx_spi_transfer_one()
977 /* Reject already-mapped transfers; PIO won't always work */ in pxa2xx_spi_transfer_one()
978 if (message->is_dma_mapped in pxa2xx_spi_transfer_one()
979 || transfer->rx_dma || transfer->tx_dma) { in pxa2xx_spi_transfer_one()
980 dev_err(&spi->dev, in pxa2xx_spi_transfer_one()
982 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
983 return -EINVAL; in pxa2xx_spi_transfer_one()
987 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
989 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
994 dev_err(&spi->dev, "Flush failed\n"); in pxa2xx_spi_transfer_one()
995 return -EIO; in pxa2xx_spi_transfer_one()
997 drv_data->n_bytes = chip->n_bytes; in pxa2xx_spi_transfer_one()
998 drv_data->tx = (void *)transfer->tx_buf; in pxa2xx_spi_transfer_one()
999 drv_data->tx_end = drv_data->tx + transfer->len; in pxa2xx_spi_transfer_one()
1000 drv_data->rx = transfer->rx_buf; in pxa2xx_spi_transfer_one()
1001 drv_data->rx_end = drv_data->rx + transfer->len; in pxa2xx_spi_transfer_one()
1002 drv_data->write = drv_data->tx ? chip->write : null_writer; in pxa2xx_spi_transfer_one()
1003 drv_data->read = drv_data->rx ? chip->read : null_reader; in pxa2xx_spi_transfer_one()
1006 bits = transfer->bits_per_word; in pxa2xx_spi_transfer_one()
1007 speed = transfer->speed_hz; in pxa2xx_spi_transfer_one()
1012 drv_data->n_bytes = 1; in pxa2xx_spi_transfer_one()
1013 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1015 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1018 drv_data->n_bytes = 2; in pxa2xx_spi_transfer_one()
1019 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1021 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1024 drv_data->n_bytes = 4; in pxa2xx_spi_transfer_one()
1025 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1027 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1034 if (chip->enable_dma) { in pxa2xx_spi_transfer_one()
1039 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
1043 dma_mapped = controller->can_dma && in pxa2xx_spi_transfer_one()
1044 controller->can_dma(controller, spi, transfer) && in pxa2xx_spi_transfer_one()
1045 controller->cur_msg_mapped; in pxa2xx_spi_transfer_one()
1049 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; in pxa2xx_spi_transfer_one()
1056 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1057 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1062 drv_data->transfer_handler = interrupt_transfer; in pxa2xx_spi_transfer_one()
1065 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1066 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1072 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1073 controller->max_speed_hz in pxa2xx_spi_transfer_one()
1077 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1078 controller->max_speed_hz / 2 in pxa2xx_spi_transfer_one()
1083 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1084 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1091 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1092 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1098 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); in pxa2xx_spi_transfer_one()
1102 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1105 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); in pxa2xx_spi_transfer_one()
1114 pxa_ssp_enable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1121 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); in pxa2xx_spi_transfer_one()
1122 if (tx_level > transfer->len) in pxa2xx_spi_transfer_one()
1123 tx_level = transfer->len; in pxa2xx_spi_transfer_one()
1124 drv_data->tx += tx_level; in pxa2xx_spi_transfer_one()
1129 while (drv_data->write(drv_data)) in pxa2xx_spi_transfer_one()
1131 if (drv_data->gpiod_ready) { in pxa2xx_spi_transfer_one()
1132 gpiod_set_value(drv_data->gpiod_ready, 1); in pxa2xx_spi_transfer_one()
1134 gpiod_set_value(drv_data->gpiod_ready, 0); in pxa2xx_spi_transfer_one()
1151 int_error_stop(drv_data, "transfer aborted", -EINTR); in pxa2xx_spi_slave_abort()
1173 if (atomic_read(&drv_data->dma_running)) in pxa2xx_spi_handle_err()
1189 if (!gpio_is_valid(spi->cs_gpio)) in cleanup_cs()
1192 gpio_free(spi->cs_gpio); in cleanup_cs()
1193 spi->cs_gpio = -ENOENT; in cleanup_cs()
1199 struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); in setup_cs()
1207 if (drv_data->ssp_type == CE4100_SSP) in setup_cs()
1216 /* If ->cs_control() is provided, ignore GPIO chip select */ in setup_cs()
1217 if (chip_info->cs_control) { in setup_cs()
1218 chip->cs_control = chip_info->cs_control; in setup_cs()
1222 if (gpio_is_valid(chip_info->gpio_cs)) { in setup_cs()
1223 int gpio = chip_info->gpio_cs; in setup_cs()
1228 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", gpio); in setup_cs()
1232 err = gpio_direction_output(gpio, !(spi->mode & SPI_CS_HIGH)); in setup_cs()
1238 spi->cs_gpio = gpio; in setup_cs()
1250 spi_controller_get_devdata(spi->controller); in setup()
1254 switch (drv_data->ssp_type) { in setup()
1277 tx_thres = config->tx_threshold_lo; in setup()
1278 tx_hi_thres = config->tx_threshold_hi; in setup()
1279 rx_thres = config->rx_threshold; in setup()
1283 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1298 return -ENOMEM; in setup()
1300 if (drv_data->ssp_type == CE4100_SSP) { in setup()
1301 if (spi->chip_select > 4) { in setup()
1302 dev_err(&spi->dev, in setup()
1305 return -EINVAL; in setup()
1308 chip->enable_dma = drv_data->controller_info->enable_dma; in setup()
1309 chip->timeout = TIMOUT_DFLT; in setup()
1316 chip_info = spi->controller_data; in setup()
1319 chip->cr1 = 0; in setup()
1321 if (chip_info->timeout) in setup()
1322 chip->timeout = chip_info->timeout; in setup()
1323 if (chip_info->tx_threshold) in setup()
1324 tx_thres = chip_info->tx_threshold; in setup()
1325 if (chip_info->tx_hi_threshold) in setup()
1326 tx_hi_thres = chip_info->tx_hi_threshold; in setup()
1327 if (chip_info->rx_threshold) in setup()
1328 rx_thres = chip_info->rx_threshold; in setup()
1329 chip->dma_threshold = 0; in setup()
1330 if (chip_info->enable_loopback) in setup()
1331 chip->cr1 = SSCR1_LBM; in setup()
1333 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1334 chip->cr1 |= SSCR1_SCFR; in setup()
1335 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1336 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1337 chip->cr1 |= SSCR1_SPH; in setup()
1341 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); in setup()
1342 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | in setup()
1347 chip->lpss_rx_threshold = rx_thres; in setup()
1348 chip->lpss_tx_threshold = tx_thres; in setup()
1352 * Set DMA burst and threshold outside of chip_info path so that if in setup()
1353 * chip_info goes away after setting chip->enable_dma, the burst and in setup()
1354 * threshold can still respond to changes in bits_per_word. in setup()
1356 if (chip->enable_dma) { in setup()
1357 /* Set up legal burst and threshold for DMA */ in setup()
1359 spi->bits_per_word, in setup()
1360 &chip->dma_burst_size, in setup()
1361 &chip->dma_threshold)) { in setup()
1362 dev_warn(&spi->dev, in setup()
1365 dev_dbg(&spi->dev, in setup()
1367 chip->dma_burst_size); in setup()
1370 switch (drv_data->ssp_type) { in setup()
1372 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
1378 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
1382 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | in setup()
1387 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1388 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | in setup()
1389 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); in setup()
1391 if (spi->mode & SPI_LOOP) in setup()
1392 chip->cr1 |= SSCR1_LBM; in setup()
1394 if (spi->bits_per_word <= 8) { in setup()
1395 chip->n_bytes = 1; in setup()
1396 chip->read = u8_reader; in setup()
1397 chip->write = u8_writer; in setup()
1398 } else if (spi->bits_per_word <= 16) { in setup()
1399 chip->n_bytes = 2; in setup()
1400 chip->read = u16_reader; in setup()
1401 chip->write = u16_writer; in setup()
1402 } else if (spi->bits_per_word <= 32) { in setup()
1403 chip->n_bytes = 4; in setup()
1404 chip->read = u32_reader; in setup()
1405 chip->write = u32_writer; in setup()
1410 if (drv_data->ssp_type == CE4100_SSP) in setup()
1447 /* SPT-LP */
1450 /* SPT-H */
1453 /* KBL-H */
1456 /* CML-V */
1459 /* BXT A-Step */
1463 /* BXT B-Step */
1471 /* ICL-LP */
1483 /* TGL-H */
1488 /* ADL-P */
1492 /* ADL-M */
1500 /* ADL-S */
1505 /* CNL-LP */
1509 /* CNL-H */
1513 /* CML-LP */
1517 /* CML-H */
1521 /* TGL-LP */
1533 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1544 int port_id = -1; in pxa2xx_spi_get_port_id()
1547 if (adev && adev->pnp.unique_id && in pxa2xx_spi_get_port_id()
1548 !kstrtouint(adev->pnp.unique_id, 0, &devid)) in pxa2xx_spi_get_port_id()
1557 return -1; in pxa2xx_spi_get_port_id()
1567 return param == chan->device->dev; in pxa2xx_spi_idma_filter()
1578 struct device *parent = pdev->dev.parent; in pxa2xx_spi_init_pdata()
1587 match = device_get_match_data(&pdev->dev); in pxa2xx_spi_init_pdata()
1591 type = (enum pxa_ssp_type)pcidev_id->driver_data; in pxa2xx_spi_init_pdata()
1593 return ERR_PTR(-EINVAL); in pxa2xx_spi_init_pdata()
1595 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in pxa2xx_spi_init_pdata()
1597 return ERR_PTR(-ENOMEM); in pxa2xx_spi_init_pdata()
1599 ssp = &pdata->ssp; in pxa2xx_spi_init_pdata()
1602 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); in pxa2xx_spi_init_pdata()
1603 if (IS_ERR(ssp->mmio_base)) in pxa2xx_spi_init_pdata()
1604 return ERR_CAST(ssp->mmio_base); in pxa2xx_spi_init_pdata()
1606 ssp->phys_base = res->start; in pxa2xx_spi_init_pdata()
1610 pdata->tx_param = parent; in pxa2xx_spi_init_pdata()
1611 pdata->rx_param = parent; in pxa2xx_spi_init_pdata()
1612 pdata->dma_filter = pxa2xx_spi_idma_filter; in pxa2xx_spi_init_pdata()
1616 ssp->clk = devm_clk_get(&pdev->dev, NULL); in pxa2xx_spi_init_pdata()
1617 if (IS_ERR(ssp->clk)) in pxa2xx_spi_init_pdata()
1618 return ERR_CAST(ssp->clk); in pxa2xx_spi_init_pdata()
1620 ssp->irq = platform_get_irq(pdev, 0); in pxa2xx_spi_init_pdata()
1621 if (ssp->irq < 0) in pxa2xx_spi_init_pdata()
1622 return ERR_PTR(ssp->irq); in pxa2xx_spi_init_pdata()
1624 ssp->type = type; in pxa2xx_spi_init_pdata()
1625 ssp->dev = &pdev->dev; in pxa2xx_spi_init_pdata()
1626 ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev); in pxa2xx_spi_init_pdata()
1628 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); in pxa2xx_spi_init_pdata()
1629 pdata->num_chipselect = 1; in pxa2xx_spi_init_pdata()
1630 pdata->enable_dma = true; in pxa2xx_spi_init_pdata()
1631 pdata->dma_burst_size = 1; in pxa2xx_spi_init_pdata()
1641 if (has_acpi_companion(drv_data->ssp->dev)) { in pxa2xx_spi_fw_translate_cs()
1642 switch (drv_data->ssp_type) { in pxa2xx_spi_fw_translate_cs()
1650 return cs - 1; in pxa2xx_spi_fw_translate_cs()
1667 struct device *dev = &pdev->dev; in pxa2xx_spi_probe()
1680 dev_err(&pdev->dev, "missing platform data\n"); in pxa2xx_spi_probe()
1685 ssp = pxa_ssp_request(pdev->id, pdev->name); in pxa2xx_spi_probe()
1687 ssp = &platform_info->ssp; in pxa2xx_spi_probe()
1689 if (!ssp->mmio_base) { in pxa2xx_spi_probe()
1690 dev_err(&pdev->dev, "failed to get SSP\n"); in pxa2xx_spi_probe()
1691 return -ENODEV; in pxa2xx_spi_probe()
1694 if (platform_info->is_slave) in pxa2xx_spi_probe()
1700 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); in pxa2xx_spi_probe()
1701 status = -ENOMEM; in pxa2xx_spi_probe()
1705 drv_data->controller = controller; in pxa2xx_spi_probe()
1706 drv_data->controller_info = platform_info; in pxa2xx_spi_probe()
1707 drv_data->ssp = ssp; in pxa2xx_spi_probe()
1709 controller->dev.of_node = dev->of_node; in pxa2xx_spi_probe()
1710 controller->dev.fwnode = dev->fwnode; in pxa2xx_spi_probe()
1712 /* The spi->mode bits understood by this driver: */ in pxa2xx_spi_probe()
1713 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pxa2xx_spi_probe()
1715 controller->bus_num = ssp->port_id; in pxa2xx_spi_probe()
1716 controller->dma_alignment = DMA_ALIGNMENT; in pxa2xx_spi_probe()
1717 controller->cleanup = cleanup; in pxa2xx_spi_probe()
1718 controller->setup = setup; in pxa2xx_spi_probe()
1719 controller->set_cs = pxa2xx_spi_set_cs; in pxa2xx_spi_probe()
1720 controller->transfer_one = pxa2xx_spi_transfer_one; in pxa2xx_spi_probe()
1721 controller->slave_abort = pxa2xx_spi_slave_abort; in pxa2xx_spi_probe()
1722 controller->handle_err = pxa2xx_spi_handle_err; in pxa2xx_spi_probe()
1723 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; in pxa2xx_spi_probe()
1724 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; in pxa2xx_spi_probe()
1725 controller->auto_runtime_pm = true; in pxa2xx_spi_probe()
1726 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in pxa2xx_spi_probe()
1728 drv_data->ssp_type = ssp->type; in pxa2xx_spi_probe()
1731 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1733 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1736 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in pxa2xx_spi_probe()
1740 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1741 drv_data->dma_cr1 = 0; in pxa2xx_spi_probe()
1742 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()
1743 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()
1745 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1746 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
1747 drv_data->dma_cr1 = DEFAULT_DMA_CR1; in pxa2xx_spi_probe()
1748 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()
1749 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS in pxa2xx_spi_probe()
1753 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), in pxa2xx_spi_probe()
1756 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); in pxa2xx_spi_probe()
1761 if (platform_info->enable_dma) { in pxa2xx_spi_probe()
1765 platform_info->enable_dma = false; in pxa2xx_spi_probe()
1767 controller->can_dma = pxa2xx_spi_can_dma; in pxa2xx_spi_probe()
1768 controller->max_dma_len = MAX_DMA_LEN; in pxa2xx_spi_probe()
1769 controller->max_transfer_size = in pxa2xx_spi_probe()
1775 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_probe()
1779 controller->max_speed_hz = clk_get_rate(ssp->clk); in pxa2xx_spi_probe()
1785 controller->min_speed_hz = in pxa2xx_spi_probe()
1786 DIV_ROUND_UP(controller->max_speed_hz, 4096); in pxa2xx_spi_probe()
1788 controller->min_speed_hz = in pxa2xx_spi_probe()
1789 DIV_ROUND_UP(controller->max_speed_hz, 512); in pxa2xx_spi_probe()
1794 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1841 if (config->reg_capabilities >= 0) { in pxa2xx_spi_probe()
1843 config->reg_capabilities); in pxa2xx_spi_probe()
1846 platform_info->num_chipselect = ffz(tmp); in pxa2xx_spi_probe()
1847 } else if (config->cs_num) { in pxa2xx_spi_probe()
1848 platform_info->num_chipselect = config->cs_num; in pxa2xx_spi_probe()
1851 controller->num_chipselect = platform_info->num_chipselect; in pxa2xx_spi_probe()
1852 controller->use_gpio_descriptors = true; in pxa2xx_spi_probe()
1854 if (platform_info->is_slave) { in pxa2xx_spi_probe()
1855 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, in pxa2xx_spi_probe()
1857 if (IS_ERR(drv_data->gpiod_ready)) { in pxa2xx_spi_probe()
1858 status = PTR_ERR(drv_data->gpiod_ready); in pxa2xx_spi_probe()
1863 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in pxa2xx_spi_probe()
1864 pm_runtime_use_autosuspend(&pdev->dev); in pxa2xx_spi_probe()
1865 pm_runtime_set_active(&pdev->dev); in pxa2xx_spi_probe()
1866 pm_runtime_enable(&pdev->dev); in pxa2xx_spi_probe()
1872 dev_err(&pdev->dev, "problem registering SPI controller\n"); in pxa2xx_spi_probe()
1879 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_probe()
1882 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_probe()
1886 free_irq(ssp->irq, drv_data); in pxa2xx_spi_probe()
1896 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_remove()
1898 pm_runtime_get_sync(&pdev->dev); in pxa2xx_spi_remove()
1900 spi_unregister_controller(drv_data->controller); in pxa2xx_spi_remove()
1904 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_remove()
1907 if (drv_data->controller_info->enable_dma) in pxa2xx_spi_remove()
1910 pm_runtime_put_noidle(&pdev->dev); in pxa2xx_spi_remove()
1911 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_remove()
1914 free_irq(ssp->irq, drv_data); in pxa2xx_spi_remove()
1926 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_suspend()
1929 status = spi_controller_suspend(drv_data->controller); in pxa2xx_spi_suspend()
1936 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_suspend()
1944 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_resume()
1949 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_resume()
1955 return spi_controller_resume(drv_data->controller); in pxa2xx_spi_resume()
1964 clk_disable_unprepare(drv_data->ssp->clk); in pxa2xx_spi_runtime_suspend()
1973 status = clk_prepare_enable(drv_data->ssp->clk); in pxa2xx_spi_runtime_resume()
1986 .name = "pxa2xx-spi",