Lines Matching +full:ls1028a +full:- +full:flexspi +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
4 * NXP FlexSPI(FSPI) controller driver.
6 * Copyright 2019-2020 NXP
9 * FlexSPI is a flexsible SPI host controller which supports two SPI
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
37 #include <linux/clk.h>
59 #include <linux/spi/spi-mem.h>
295 #define LUT_PAD(x) (fls(x) - 1)
301 * ---------------------------------------------------
303 * ---------------------------------------------------
337 .little_endian = true, /* little-endian */
345 .little_endian = true, /* little-endian */
353 .little_endian = true, /* little-endian */
361 .little_endian = true, /* little-endian */
371 struct clk *clk, *clk_en; member
382 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; in needs_ip_only()
386 * R/W functions for big- or little-endian registers:
389 * core is little-endian the FSPI controller can use
390 * big-endian or little-endian.
394 if (f->devtype_data->little_endian) in fspi_writel()
402 if (f->devtype_data->little_endian) in fspi_readl()
414 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
415 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
418 complete(&f->c); in nxp_fspi_irq_handler()
433 return -ENOTSUPP; in nxp_fspi_check_buswidth()
439 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); in nxp_fspi_supports_op()
442 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); in nxp_fspi_supports_op()
444 if (op->addr.nbytes) in nxp_fspi_supports_op()
445 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); in nxp_fspi_supports_op()
447 if (op->dummy.nbytes) in nxp_fspi_supports_op()
448 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); in nxp_fspi_supports_op()
450 if (op->data.nbytes) in nxp_fspi_supports_op()
451 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); in nxp_fspi_supports_op()
459 if (op->addr.nbytes > 4) in nxp_fspi_supports_op()
467 if (op->addr.val >= f->memmap_phy_size) in nxp_fspi_supports_op()
471 if (op->dummy.buswidth && in nxp_fspi_supports_op()
472 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) in nxp_fspi_supports_op()
476 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_supports_op()
477 (op->data.nbytes > f->devtype_data->ahb_buf_size || in nxp_fspi_supports_op()
478 (op->data.nbytes > f->devtype_data->rxfifo - 4 && in nxp_fspi_supports_op()
479 !IS_ALIGNED(op->data.nbytes, 8)))) in nxp_fspi_supports_op()
482 if (op->data.dir == SPI_MEM_DATA_OUT && in nxp_fspi_supports_op()
483 op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_supports_op()
496 if (!f->devtype_data->little_endian) in fspi_readl_poll_tout()
517 reg = fspi_readl(f, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
518 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
521 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_invalid()
529 void __iomem *base = f->iobase; in nxp_fspi_prepare_lut()
534 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), in nxp_fspi_prepare_lut()
535 op->cmd.opcode); in nxp_fspi_prepare_lut()
538 if (op->addr.nbytes) { in nxp_fspi_prepare_lut()
540 LUT_PAD(op->addr.buswidth), in nxp_fspi_prepare_lut()
541 op->addr.nbytes * 8); in nxp_fspi_prepare_lut()
546 if (op->dummy.nbytes) { in nxp_fspi_prepare_lut()
549 * Due to FlexSPI controller limitation number of PAD for dummy in nxp_fspi_prepare_lut()
552 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
553 op->dummy.nbytes * 8 / in nxp_fspi_prepare_lut()
554 op->dummy.buswidth); in nxp_fspi_prepare_lut()
559 if (op->data.nbytes) { in nxp_fspi_prepare_lut()
561 op->data.dir == SPI_MEM_DATA_IN ? in nxp_fspi_prepare_lut()
563 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
572 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
573 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
579 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", in nxp_fspi_prepare_lut()
580 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); in nxp_fspi_prepare_lut()
583 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
584 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
591 if (is_acpi_node(f->dev->fwnode)) in nxp_fspi_clk_prep_enable()
594 ret = clk_prepare_enable(f->clk_en); in nxp_fspi_clk_prep_enable()
598 ret = clk_prepare_enable(f->clk); in nxp_fspi_clk_prep_enable()
600 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_prep_enable()
609 if (is_acpi_node(f->dev->fwnode)) in nxp_fspi_clk_disable_unprep()
612 clk_disable_unprepare(f->clk); in nxp_fspi_clk_disable_unprep()
613 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_disable_unprep()
619 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
623 * -------- <-- FLSHB2CR0
626 * B2 start address --> -------- <-- FLSHB1CR0
629 * B1 start address --> -------- <-- FLSHA2CR0
632 * A2 start address --> -------- <-- FLSHA1CR0
635 * A1 start address --> -------- (Lower address)
649 * chip-select Flash configuration register.
658 unsigned long rate = spi->max_speed_hz; in nxp_fspi_select_mem()
666 if (f->selected == spi->chip_select) in nxp_fspi_select_mem()
670 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); in nxp_fspi_select_mem()
671 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); in nxp_fspi_select_mem()
672 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); in nxp_fspi_select_mem()
673 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); in nxp_fspi_select_mem()
676 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); in nxp_fspi_select_mem()
678 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + in nxp_fspi_select_mem()
679 4 * spi->chip_select); in nxp_fspi_select_mem()
681 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); in nxp_fspi_select_mem()
685 ret = clk_set_rate(f->clk, rate); in nxp_fspi_select_mem()
693 f->selected = spi->chip_select; in nxp_fspi_select_mem()
698 u32 start = op->addr.val; in nxp_fspi_read_ahb()
699 u32 len = op->data.nbytes; in nxp_fspi_read_ahb()
702 if ((!f->ahb_addr) || start < f->memmap_start || in nxp_fspi_read_ahb()
703 start + len > f->memmap_start + f->memmap_len) { in nxp_fspi_read_ahb()
704 if (f->ahb_addr) in nxp_fspi_read_ahb()
705 iounmap(f->ahb_addr); in nxp_fspi_read_ahb()
707 f->memmap_start = start; in nxp_fspi_read_ahb()
708 f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? in nxp_fspi_read_ahb()
711 f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, in nxp_fspi_read_ahb()
712 f->memmap_len); in nxp_fspi_read_ahb()
714 if (!f->ahb_addr) { in nxp_fspi_read_ahb()
715 dev_err(f->dev, "failed to alloc memory\n"); in nxp_fspi_read_ahb()
716 return -ENOMEM; in nxp_fspi_read_ahb()
721 memcpy_fromio(op->data.buf.in, in nxp_fspi_read_ahb()
722 f->ahb_addr + start - f->memmap_start, len); in nxp_fspi_read_ahb()
730 void __iomem *base = f->iobase; in nxp_fspi_fill_txfifo()
732 u8 *buf = (u8 *) op->data.buf.out; in nxp_fspi_fill_txfifo()
742 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { in nxp_fspi_fill_txfifo()
744 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
754 if (i < op->data.nbytes) { in nxp_fspi_fill_txfifo()
758 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
763 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { in nxp_fspi_fill_txfifo()
774 void __iomem *base = f->iobase; in nxp_fspi_read_rxfifo()
776 int len = op->data.nbytes; in nxp_fspi_read_rxfifo()
777 u8 *buf = (u8 *) op->data.buf.in; in nxp_fspi_read_rxfifo()
785 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
800 buf = op->data.buf.in + i; in nxp_fspi_read_rxfifo()
802 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
807 len = op->data.nbytes - i; in nxp_fspi_read_rxfifo()
808 for (j = 0; j < op->data.nbytes - i; j += 4) { in nxp_fspi_read_rxfifo()
812 len -= size; in nxp_fspi_read_rxfifo()
824 void __iomem *base = f->iobase; in nxp_fspi_do_op()
835 init_completion(&f->c); in nxp_fspi_do_op()
837 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); in nxp_fspi_do_op()
843 fspi_writel(f, op->data.nbytes | in nxp_fspi_do_op()
852 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) in nxp_fspi_do_op()
853 err = -ETIMEDOUT; in nxp_fspi_do_op()
856 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) in nxp_fspi_do_op()
864 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); in nxp_fspi_exec_op()
867 mutex_lock(&f->lock); in nxp_fspi_exec_op()
870 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, in nxp_fspi_exec_op()
874 nxp_fspi_select_mem(f, mem->spi); in nxp_fspi_exec_op()
883 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && in nxp_fspi_exec_op()
884 op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_exec_op()
888 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in nxp_fspi_exec_op()
897 mutex_unlock(&f->lock); in nxp_fspi_exec_op()
904 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); in nxp_fspi_adjust_op_size()
906 if (op->data.dir == SPI_MEM_DATA_OUT) { in nxp_fspi_adjust_op_size()
907 if (op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_adjust_op_size()
908 op->data.nbytes = f->devtype_data->txfifo; in nxp_fspi_adjust_op_size()
910 if (op->data.nbytes > f->devtype_data->ahb_buf_size) in nxp_fspi_adjust_op_size()
911 op->data.nbytes = f->devtype_data->ahb_buf_size; in nxp_fspi_adjust_op_size()
912 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) in nxp_fspi_adjust_op_size()
913 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); in nxp_fspi_adjust_op_size()
917 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_adjust_op_size()
919 op->data.nbytes > f->devtype_data->rxfifo) in nxp_fspi_adjust_op_size()
920 op->data.nbytes = f->devtype_data->rxfifo; in nxp_fspi_adjust_op_size()
928 { .family = "QorIQ LS1028A" }, in erratum_err050568()
935 /* Check for LS1028A family */ in erratum_err050568()
937 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); in erratum_err050568()
941 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); in erratum_err050568()
943 dev_err(f->dev, "No syscon regmap\n"); in erratum_err050568()
952 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); in erratum_err050568()
956 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; in erratum_err050568()
961 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); in erratum_err050568()
966 void __iomem *base = f->iobase; in nxp_fspi_default_setup()
974 ret = clk_set_rate(f->clk, 20000000); in nxp_fspi_default_setup()
983 * ERR050568: Flash access by FlexSPI AHB command may not work with in nxp_fspi_default_setup()
984 * platform frequency equal to 300 MHz on LS1028A. in nxp_fspi_default_setup()
985 * LS1028A reuses LX2160A compatible entry. Make errata applicable for in nxp_fspi_default_setup()
986 * Layerscape LS1028A platform. in nxp_fspi_default_setup()
988 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) in nxp_fspi_default_setup()
993 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_default_setup()
1013 reg = fspi_readl(f, f->iobase + FSPI_MCR2); in nxp_fspi_default_setup()
1025 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | in nxp_fspi_default_setup()
1032 /* AHB Read - Set lut sequence ID for all CS. */ in nxp_fspi_default_setup()
1038 f->selected = -1; in nxp_fspi_default_setup()
1048 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); in nxp_fspi_get_name()
1049 struct device *dev = &mem->spi->dev; in nxp_fspi_get_name()
1053 if (of_get_available_child_count(f->dev->of_node) == 1) in nxp_fspi_get_name()
1054 return dev_name(f->dev); in nxp_fspi_get_name()
1057 "%s-%d", dev_name(f->dev), in nxp_fspi_get_name()
1058 mem->spi->chip_select); in nxp_fspi_get_name()
1062 return ERR_PTR(-ENOMEM); in nxp_fspi_get_name()
1078 struct device *dev = &pdev->dev; in nxp_fspi_probe()
1079 struct device_node *np = dev->of_node; in nxp_fspi_probe()
1085 ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); in nxp_fspi_probe()
1087 return -ENOMEM; in nxp_fspi_probe()
1089 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | in nxp_fspi_probe()
1093 f->dev = dev; in nxp_fspi_probe()
1094 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); in nxp_fspi_probe()
1095 if (!f->devtype_data) { in nxp_fspi_probe()
1096 ret = -ENODEV; in nxp_fspi_probe()
1102 /* find the resources - configuration register address space */ in nxp_fspi_probe()
1103 if (is_acpi_node(f->dev->fwnode)) in nxp_fspi_probe()
1109 f->iobase = devm_ioremap_resource(dev, res); in nxp_fspi_probe()
1110 if (IS_ERR(f->iobase)) { in nxp_fspi_probe()
1111 ret = PTR_ERR(f->iobase); in nxp_fspi_probe()
1115 /* find the resources - controller memory mapped space */ in nxp_fspi_probe()
1116 if (is_acpi_node(f->dev->fwnode)) in nxp_fspi_probe()
1123 ret = -ENODEV; in nxp_fspi_probe()
1128 f->memmap_phy = res->start; in nxp_fspi_probe()
1129 f->memmap_phy_size = resource_size(res); in nxp_fspi_probe()
1132 if (dev_of_node(&pdev->dev)) { in nxp_fspi_probe()
1133 f->clk_en = devm_clk_get(dev, "fspi_en"); in nxp_fspi_probe()
1134 if (IS_ERR(f->clk_en)) { in nxp_fspi_probe()
1135 ret = PTR_ERR(f->clk_en); in nxp_fspi_probe()
1139 f->clk = devm_clk_get(dev, "fspi"); in nxp_fspi_probe()
1140 if (IS_ERR(f->clk)) { in nxp_fspi_probe()
1141 ret = PTR_ERR(f->clk); in nxp_fspi_probe()
1153 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1155 fspi_writel(f, reg, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1163 nxp_fspi_irq_handler, 0, pdev->name, f); in nxp_fspi_probe()
1169 mutex_init(&f->lock); in nxp_fspi_probe()
1171 ctlr->bus_num = -1; in nxp_fspi_probe()
1172 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; in nxp_fspi_probe()
1173 ctlr->mem_ops = &nxp_fspi_mem_ops; in nxp_fspi_probe()
1177 ctlr->dev.of_node = np; in nxp_fspi_probe()
1179 ret = devm_spi_register_controller(&pdev->dev, ctlr); in nxp_fspi_probe()
1186 mutex_destroy(&f->lock); in nxp_fspi_probe()
1203 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); in nxp_fspi_remove()
1207 mutex_destroy(&f->lock); in nxp_fspi_remove()
1209 if (f->ahb_addr) in nxp_fspi_remove()
1210 iounmap(f->ahb_addr); in nxp_fspi_remove()
1230 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1231 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1232 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, },
1233 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1234 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, },
1254 .name = "nxp-fspi",