12 #include <linux/qcom-geni-se.h>
16 /* SPI SE specific registers and respective register fields */
67 	struct geni_se se;  member
98 	ret = geni_se_clk_freq_match(&mas->se,  in get_spi_clk_cfg()
126 	struct geni_se *se = &mas->se;  in handle_fifo_timeout()  local
130 	writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in handle_fifo_timeout()
132 	geni_se_cancel_m_cmd(se);  in handle_fifo_timeout()
141 	geni_se_abort_m_cmd(se);  in handle_fifo_timeout()
158 	struct geni_se *se = &mas->se;  in spi_geni_is_abort_still_pending()  local
171 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in spi_geni_is_abort_still_pending()
172 	m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);  in spi_geni_is_abort_still_pending()
194 	struct geni_se *se = &mas->se;  in spi_geni_set_cs()  local
220 		geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);  in spi_geni_set_cs()
222 		geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);  in spi_geni_set_cs()
240 	struct geni_se *se = &mas->se;  in spi_setup_word_len()  local
251 	geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,  in spi_setup_word_len()
254 	writel(word_len, se->base + SE_SPI_WORD_LEN);  in spi_setup_word_len()
261 	struct geni_se *se = &mas->se;  in geni_spi_set_clock_and_bw()  local
284 	writel(clk_sel, se->base + SE_GENI_CLK_SEL);  in geni_spi_set_clock_and_bw()
285 	writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);  in geni_spi_set_clock_and_bw()
288 	se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);  in geni_spi_set_clock_and_bw()
289 	ret = geni_icc_set_bw(se);  in geni_spi_set_clock_and_bw()
300 	struct geni_se *se = &mas->se;  in setup_fifo_params()  local
321 		writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);  in setup_fifo_params()
322 		writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);  in setup_fifo_params()
323 		writel(cpha, se->base + SE_SPI_CPHA);  in setup_fifo_params()
324 		writel(cpol, se->base + SE_SPI_CPOL);  in setup_fifo_params()
325 		writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);  in setup_fifo_params()
350 	struct geni_se *se = &mas->se;  in spi_geni_init()  local
356 	proto = geni_se_read_proto(se);  in spi_geni_init()
362 	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);  in spi_geni_init()
365 	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);  in spi_geni_init()
371 	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);  in spi_geni_init()
374 	ver = geni_se_get_qup_hw_version(se);  in spi_geni_init()
383 	geni_se_select_mode(se, GENI_SE_FIFO);  in spi_geni_init()
386 	spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
388 	writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
410 	struct geni_se *se = &mas->se;  in geni_spi_handle_tx()  local
418 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
436 		iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);  in geni_spi_handle_tx()
440 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
448 	struct geni_se *se = &mas->se;  in geni_spi_handle_rx()  local
456 	rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);  in geni_spi_handle_rx()
468 			readl(se->base + SE_GENI_RX_FIFOn);  in geni_spi_handle_rx()
483 		ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);  in geni_spi_handle_rx()
496 	struct geni_se *se = &mas->se;  in setup_fifo_xfer()  local
537 		writel(len, se->base + SE_SPI_TX_TRANS_LEN);  in setup_fifo_xfer()
542 		writel(len, se->base + SE_SPI_RX_TRANS_LEN);  in setup_fifo_xfer()
551 	geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);  in setup_fifo_xfer()
554 			writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);  in setup_fifo_xfer()
580 	struct geni_se *se = &mas->se;  in geni_spi_isr()  local
583 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in geni_spi_isr()
618 				writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_isr()
648 	writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_spi_isr()
672 	clk = devm_clk_get(dev, "se");  in spi_geni_probe()
684 	mas->se.dev = dev;  in spi_geni_probe()
685 	mas->se.wrapper = dev_get_drvdata(dev->parent);  in spi_geni_probe()
686 	mas->se.base = base;  in spi_geni_probe()
687 	mas->se.clk = clk;  in spi_geni_probe()
689 	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");  in spi_geni_probe()
720 	ret = geni_icc_get(&mas->se, NULL);  in spi_geni_probe()
724 	mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);  in spi_geni_probe()
725 	mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in spi_geni_probe()
727 	ret = geni_icc_set_bw(&mas->se);  in spi_geni_probe()
773 	ret = geni_se_resources_off(&mas->se);  in spi_geni_runtime_suspend()
777 	return geni_icc_disable(&mas->se);  in spi_geni_runtime_suspend()
786 	ret = geni_icc_enable(&mas->se);  in spi_geni_runtime_resume()
790 	ret = geni_se_resources_on(&mas->se);  in spi_geni_runtime_resume()