Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
12 #include <linux/qcom-geni-se.h>
98 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
99 speed_hz * mas->oversampling, in get_spi_clk_cfg()
102 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
107 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
108 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
110 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
112 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
114 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
116 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
126 struct geni_se *se = &mas->se; in handle_fifo_timeout()
128 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
129 reinit_completion(&mas->cancel_done); in handle_fifo_timeout()
130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
131 mas->cur_xfer = NULL; in handle_fifo_timeout()
133 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
135 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_fifo_timeout()
139 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
140 reinit_completion(&mas->abort_done); in handle_fifo_timeout()
142 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
144 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_fifo_timeout()
146 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_fifo_timeout()
152 mas->abort_failed = true; in handle_fifo_timeout()
158 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending()
161 if (!mas->abort_failed) in spi_geni_is_abort_still_pending()
170 spin_lock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
173 spin_unlock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
176 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", in spi_geni_is_abort_still_pending()
185 mas->abort_failed = false; in spi_geni_is_abort_still_pending()
192 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in spi_geni_set_cs()
193 struct spi_master *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs()
194 struct geni_se *se = &mas->se; in spi_geni_set_cs()
197 if (!(slv->mode & SPI_CS_HIGH)) in spi_geni_set_cs()
200 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
203 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
206 dev_err(mas->dev, "Can't set chip select\n"); in spi_geni_set_cs()
210 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
211 if (mas->cur_xfer) { in spi_geni_set_cs()
212 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); in spi_geni_set_cs()
213 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
217 mas->cs_flag = set_flag; in spi_geni_set_cs()
218 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
223 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
225 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
227 dev_warn(mas->dev, "Timeout setting chip select\n"); in spi_geni_set_cs()
232 pm_runtime_put(mas->dev); in spi_geni_set_cs()
240 struct geni_se *se = &mas->se; in spi_setup_word_len()
244 * If bits_per_word isn't a byte aligned value, set the packing to be in spi_setup_word_len()
245 * 1 SPI word per FIFO word. in spi_setup_word_len()
247 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
248 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
251 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
253 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; in spi_setup_word_len()
254 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
261 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw()
264 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
269 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
280 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
284 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
285 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
287 /* Set BW quota for CPU as driver supports FIFO mode only. */ in geni_spi_set_clock_and_bw()
288 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
300 struct geni_se *se = &mas->se; in setup_fifo_params()
304 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
305 if (spi_slv->mode & SPI_LOOP) in setup_fifo_params()
308 if (spi_slv->mode & SPI_CPOL) in setup_fifo_params()
311 if (spi_slv->mode & SPI_CPHA) in setup_fifo_params()
314 if (spi_slv->mode & SPI_CS_HIGH) in setup_fifo_params()
315 demux_output_inv = BIT(spi_slv->chip_select); in setup_fifo_params()
317 demux_sel = spi_slv->chip_select; in setup_fifo_params()
318 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
320 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
321 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
322 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
323 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
324 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
325 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
327 mas->last_mode = spi_slv->mode; in setup_fifo_params()
330 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
340 return -EBUSY; in spi_geni_prepare_message()
342 ret = setup_fifo_params(spi_msg->spi, spi); in spi_geni_prepare_message()
344 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
350 struct geni_se *se = &mas->se; in spi_geni_init()
354 pm_runtime_get_sync(mas->dev); in spi_geni_init()
358 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
359 pm_runtime_put(mas->dev); in spi_geni_init()
360 return -ENXIO; in spi_geni_init()
362 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
364 /* Width of Tx and Rx FIFO is same */ in spi_geni_init()
365 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
369 * RX FIFO RFR level to fifo_depth-2. in spi_geni_init()
371 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
372 /* Transmit an entire FIFO worth of data per IRQ */ in spi_geni_init()
373 mas->tx_wm = 1; in spi_geni_init()
379 mas->oversampling = 2; in spi_geni_init()
381 mas->oversampling = 1; in spi_geni_init()
386 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
388 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
390 pm_runtime_put(mas->dev); in spi_geni_init()
397 * Calculate how many bytes we'll put in each FIFO word. If the in geni_byte_per_fifo_word()
398 * transfer words don't pack cleanly into a FIFO word we'll just put in geni_byte_per_fifo_word()
399 * one transfer word in each FIFO word. If they do pack we'll pack 'em. in geni_byte_per_fifo_word()
401 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
402 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
405 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
410 struct geni_se *se = &mas->se; in geni_spi_handle_tx()
416 /* Stop the watermark IRQ if nothing to send */ in geni_spi_handle_tx()
417 if (!mas->cur_xfer) { in geni_spi_handle_tx()
418 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
422 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
423 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
424 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
426 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
433 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); in geni_spi_handle_tx()
436 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
438 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
439 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
440 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
448 struct geni_se *se = &mas->se; in geni_spi_handle_rx()
456 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
462 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; in geni_spi_handle_rx()
465 /* Clear out the FIFO and bail if nowhere to put it */ in geni_spi_handle_rx()
466 if (!mas->cur_xfer) { in geni_spi_handle_rx()
468 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
472 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
473 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
475 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
482 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); in geni_spi_handle_rx()
483 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
487 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
496 struct geni_se *se = &mas->se; in setup_fifo_xfer()
511 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
512 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
514 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_fifo_xfer()
515 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_fifo_xfer()
516 mas->cur_bits_per_word = xfer->bits_per_word; in setup_fifo_xfer()
520 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_fifo_xfer()
524 mas->tx_rem_bytes = 0; in setup_fifo_xfer()
525 mas->rx_rem_bytes = 0; in setup_fifo_xfer()
527 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in setup_fifo_xfer()
528 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in setup_fifo_xfer()
530 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in setup_fifo_xfer()
533 mas->cur_xfer = xfer; in setup_fifo_xfer()
534 if (xfer->tx_buf) { in setup_fifo_xfer()
536 mas->tx_rem_bytes = xfer->len; in setup_fifo_xfer()
537 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_fifo_xfer()
540 if (xfer->rx_buf) { in setup_fifo_xfer()
542 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_fifo_xfer()
543 mas->rx_rem_bytes = xfer->len; in setup_fifo_xfer()
550 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
554 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_fifo_xfer()
556 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
566 return -EBUSY; in spi_geni_transfer_one()
569 if (!xfer->len) in spi_geni_transfer_one()
572 setup_fifo_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
580 struct geni_se *se = &mas->se; in geni_spi_isr()
583 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
590 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
592 spin_lock(&mas->lock); in geni_spi_isr()
601 if (mas->cur_xfer) { in geni_spi_isr()
603 mas->cur_xfer = NULL; in geni_spi_isr()
617 if (mas->tx_rem_bytes) { in geni_spi_isr()
618 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
619 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
620 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
622 if (mas->rx_rem_bytes) in geni_spi_isr()
623 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
624 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
626 complete(&mas->cs_done); in geni_spi_isr()
631 complete(&mas->cancel_done); in geni_spi_isr()
633 complete(&mas->abort_done); in geni_spi_isr()
638 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and in geni_spi_isr()
643 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear in geni_spi_isr()
646 * since they'll re-assert if they're still happening. in geni_spi_isr()
648 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
650 spin_unlock(&mas->lock); in geni_spi_isr()
662 struct device *dev = &pdev->dev; in spi_geni_probe()
678 return -ENOMEM; in spi_geni_probe()
682 mas->irq = irq; in spi_geni_probe()
683 mas->dev = dev; in spi_geni_probe()
684 mas->se.dev = dev; in spi_geni_probe()
685 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
686 mas->se.base = base; in spi_geni_probe()
687 mas->se.clk = clk; in spi_geni_probe()
689 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
693 ret = devm_pm_opp_of_add_table(&pdev->dev); in spi_geni_probe()
694 if (ret && ret != -ENODEV) { in spi_geni_probe()
695 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in spi_geni_probe()
699 spi->bus_num = -1; in spi_geni_probe()
700 spi->dev.of_node = dev->of_node; in spi_geni_probe()
701 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; in spi_geni_probe()
702 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_geni_probe()
703 spi->num_chipselect = 4; in spi_geni_probe()
704 spi->max_speed_hz = 50000000; in spi_geni_probe()
705 spi->prepare_message = spi_geni_prepare_message; in spi_geni_probe()
706 spi->transfer_one = spi_geni_transfer_one; in spi_geni_probe()
707 spi->auto_runtime_pm = true; in spi_geni_probe()
708 spi->handle_err = handle_fifo_timeout; in spi_geni_probe()
709 spi->set_cs = spi_geni_set_cs; in spi_geni_probe()
710 spi->use_gpio_descriptors = true; in spi_geni_probe()
712 init_completion(&mas->cs_done); in spi_geni_probe()
713 init_completion(&mas->cancel_done); in spi_geni_probe()
714 init_completion(&mas->abort_done); in spi_geni_probe()
715 spin_lock_init(&mas->lock); in spi_geni_probe()
716 pm_runtime_use_autosuspend(&pdev->dev); in spi_geni_probe()
717 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); in spi_geni_probe()
720 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
724 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
725 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
727 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
735 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
745 free_irq(mas->irq, spi); in spi_geni_probe()
759 free_irq(mas->irq, spi); in spi_geni_remove()
760 pm_runtime_disable(&pdev->dev); in spi_geni_remove()
773 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
777 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
786 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
790 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
794 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()
836 { .compatible = "qcom,geni-spi" },