1 // SPDX-License-Identifier: GPL-2.0
11  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
24 #include <linux/spi/spi-mem.h>
68 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
227 	u32 value = readl_relaxed(aq->regs + offset);  in atmel_qspi_read()
232 	dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,  in atmel_qspi_read()
244 	dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,  in atmel_qspi_write()
248 	writel_relaxed(value, aq->regs + offset);  in atmel_qspi_write()
254 	if (op->cmd.buswidth != mode->cmd_buswidth)  in atmel_qspi_is_compatible()
257 	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)  in atmel_qspi_is_compatible()
260 	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)  in atmel_qspi_is_compatible()
274 	return -ENOTSUPP;  in atmel_qspi_find_mode()
284 	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&  in atmel_qspi_supports_op()
285 		op->dummy.nbytes == 0)  in atmel_qspi_supports_op()
289 	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)  in atmel_qspi_supports_op()
291 	if (op->cmd.nbytes != 1)  in atmel_qspi_supports_op()
305 	icr = QSPI_ICR_INST(op->cmd.opcode);  in atmel_qspi_set_cfg()
313 	if (op->dummy.buswidth && op->dummy.nbytes)  in atmel_qspi_set_cfg()
314 		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;  in atmel_qspi_set_cfg()
317 	 * The controller allows 24 and 32-bit addressing while NAND-flash  in atmel_qspi_set_cfg()
318 	 * requires 16-bit long. Handling 8-bit long addresses is done using  in atmel_qspi_set_cfg()
319 	 * the option field. For the 16-bit addresses, the workaround depends  in atmel_qspi_set_cfg()
324 	 * use the same buswidth). The limitation is when the 16-bit address is  in atmel_qspi_set_cfg()
328 	if (op->addr.buswidth) {  in atmel_qspi_set_cfg()
329 		switch (op->addr.nbytes) {  in atmel_qspi_set_cfg()
334 			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);  in atmel_qspi_set_cfg()
337 			if (dummy_cycles < 8 / op->addr.buswidth) {  in atmel_qspi_set_cfg()
340 				iar = (op->cmd.opcode << 16) |  in atmel_qspi_set_cfg()
341 					(op->addr.val & 0xffff);  in atmel_qspi_set_cfg()
344 				iar = (op->addr.val << 8) & 0xffffff;  in atmel_qspi_set_cfg()
345 				dummy_cycles -= 8 / op->addr.buswidth;  in atmel_qspi_set_cfg()
350 			iar = op->addr.val & 0xffffff;  in atmel_qspi_set_cfg()
354 			iar = op->addr.val & 0x7ffffff;  in atmel_qspi_set_cfg()
357 			return -ENOTSUPP;  in atmel_qspi_set_cfg()
361 	/* offset of the data access in the QSPI memory space */  in atmel_qspi_set_cfg()
369 	if (op->data.nbytes) {  in atmel_qspi_set_cfg()
372 		if (op->addr.nbytes)  in atmel_qspi_set_cfg()
378 	 * Serial Memory Mode (SMM).  in atmel_qspi_set_cfg()
380 	if (aq->mr != QSPI_MR_SMM) {  in atmel_qspi_set_cfg()
382 		aq->mr = QSPI_MR_SMM;  in atmel_qspi_set_cfg()
389 	if (op->addr.nbytes && !op->data.nbytes)  in atmel_qspi_set_cfg()
392 	if (aq->caps->has_ricr) {  in atmel_qspi_set_cfg()
393 		if (op->data.dir == SPI_MEM_DATA_IN)  in atmel_qspi_set_cfg()
398 		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)  in atmel_qspi_set_cfg()
411 	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);  in atmel_qspi_exec_op()
418 	 * when the flash memories overrun the controller's memory space.  in atmel_qspi_exec_op()
420 	if (op->addr.val + op->data.nbytes > aq->mmap_size)  in atmel_qspi_exec_op()
421 		return -ENOTSUPP;  in atmel_qspi_exec_op()
428 	if (op->data.nbytes) {  in atmel_qspi_exec_op()
433 		if (op->data.dir == SPI_MEM_DATA_IN)  in atmel_qspi_exec_op()
434 			memcpy_fromio(op->data.buf.in, aq->mem + offset,  in atmel_qspi_exec_op()
435 				      op->data.nbytes);  in atmel_qspi_exec_op()
437 			memcpy_toio(aq->mem + offset, op->data.buf.out,  in atmel_qspi_exec_op()
438 				    op->data.nbytes);  in atmel_qspi_exec_op()
440 		/* Release the chip-select */  in atmel_qspi_exec_op()
450 	reinit_completion(&aq->cmd_completion);  in atmel_qspi_exec_op()
451 	aq->pending = sr & QSPI_SR_CMD_COMPLETED;  in atmel_qspi_exec_op()
453 	if (!wait_for_completion_timeout(&aq->cmd_completion,  in atmel_qspi_exec_op()
455 		err = -ETIMEDOUT;  in atmel_qspi_exec_op()
463 	return dev_name(spimem->spi->dev.parent);  in atmel_qspi_get_name()
474 	struct spi_controller *ctrl = spi->master;  in atmel_qspi_setup()
479 	if (ctrl->busy)  in atmel_qspi_setup()
480 		return -EBUSY;  in atmel_qspi_setup()
482 	if (!spi->max_speed_hz)  in atmel_qspi_setup()
483 		return -EINVAL;  in atmel_qspi_setup()
485 	src_rate = clk_get_rate(aq->pclk);  in atmel_qspi_setup()
487 		return -EINVAL;  in atmel_qspi_setup()
490 	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);  in atmel_qspi_setup()
492 		scbr--;  in atmel_qspi_setup()
494 	aq->scr = QSPI_SCR_SCBR(scbr);  in atmel_qspi_setup()
495 	atmel_qspi_write(aq->scr, aq, QSPI_SCR);  in atmel_qspi_setup()
505 	/* Set the QSPI controller by default in Serial Memory Mode */  in atmel_qspi_init()
507 	aq->mr = QSPI_MR_SMM;  in atmel_qspi_init()
525 	aq->pending |= pending;  in atmel_qspi_interrupt()
526 	if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)  in atmel_qspi_interrupt()
527 		complete(&aq->cmd_completion);  in atmel_qspi_interrupt()
539 	ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));  in atmel_qspi_probe()
541 		return -ENOMEM;  in atmel_qspi_probe()
543 	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;  in atmel_qspi_probe()
544 	ctrl->setup = atmel_qspi_setup;  in atmel_qspi_probe()
545 	ctrl->bus_num = -1;  in atmel_qspi_probe()
546 	ctrl->mem_ops = &atmel_qspi_mem_ops;  in atmel_qspi_probe()
547 	ctrl->num_chipselect = 1;  in atmel_qspi_probe()
548 	ctrl->dev.of_node = pdev->dev.of_node;  in atmel_qspi_probe()
553 	init_completion(&aq->cmd_completion);  in atmel_qspi_probe()
554 	aq->pdev = pdev;  in atmel_qspi_probe()
558 	aq->regs = devm_ioremap_resource(&pdev->dev, res);  in atmel_qspi_probe()
559 	if (IS_ERR(aq->regs)) {  in atmel_qspi_probe()
560 		dev_err(&pdev->dev, "missing registers\n");  in atmel_qspi_probe()
561 		return PTR_ERR(aq->regs);  in atmel_qspi_probe()
564 	/* Map the AHB memory */  in atmel_qspi_probe()
566 	aq->mem = devm_ioremap_resource(&pdev->dev, res);  in atmel_qspi_probe()
567 	if (IS_ERR(aq->mem)) {  in atmel_qspi_probe()
568 		dev_err(&pdev->dev, "missing AHB memory\n");  in atmel_qspi_probe()
569 		return PTR_ERR(aq->mem);  in atmel_qspi_probe()
572 	aq->mmap_size = resource_size(res);  in atmel_qspi_probe()
575 	aq->pclk = devm_clk_get(&pdev->dev, "pclk");  in atmel_qspi_probe()
576 	if (IS_ERR(aq->pclk))  in atmel_qspi_probe()
577 		aq->pclk = devm_clk_get(&pdev->dev, NULL);  in atmel_qspi_probe()
579 	if (IS_ERR(aq->pclk)) {  in atmel_qspi_probe()
580 		dev_err(&pdev->dev, "missing peripheral clock\n");  in atmel_qspi_probe()
581 		return PTR_ERR(aq->pclk);  in atmel_qspi_probe()
585 	err = clk_prepare_enable(aq->pclk);  in atmel_qspi_probe()
587 		dev_err(&pdev->dev, "failed to enable the peripheral clock\n");  in atmel_qspi_probe()
591 	aq->caps = of_device_get_match_data(&pdev->dev);  in atmel_qspi_probe()
592 	if (!aq->caps) {  in atmel_qspi_probe()
593 		dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");  in atmel_qspi_probe()
594 		err = -EINVAL;  in atmel_qspi_probe()
598 	if (aq->caps->has_qspick) {  in atmel_qspi_probe()
600 		aq->qspick = devm_clk_get(&pdev->dev, "qspick");  in atmel_qspi_probe()
601 		if (IS_ERR(aq->qspick)) {  in atmel_qspi_probe()
602 			dev_err(&pdev->dev, "missing system clock\n");  in atmel_qspi_probe()
603 			err = PTR_ERR(aq->qspick);  in atmel_qspi_probe()
608 		err = clk_prepare_enable(aq->qspick);  in atmel_qspi_probe()
610 			dev_err(&pdev->dev,  in atmel_qspi_probe()
622 	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,  in atmel_qspi_probe()
623 			       0, dev_name(&pdev->dev), aq);  in atmel_qspi_probe()
636 	clk_disable_unprepare(aq->qspick);  in atmel_qspi_probe()
638 	clk_disable_unprepare(aq->pclk);  in atmel_qspi_probe()
650 	clk_disable_unprepare(aq->qspick);  in atmel_qspi_remove()
651 	clk_disable_unprepare(aq->pclk);  in atmel_qspi_remove()
661 	clk_disable_unprepare(aq->qspick);  in atmel_qspi_suspend()
662 	clk_disable_unprepare(aq->pclk);  in atmel_qspi_suspend()
672 	clk_prepare_enable(aq->pclk);  in atmel_qspi_resume()
673 	clk_prepare_enable(aq->qspick);  in atmel_qspi_resume()
677 	atmel_qspi_write(aq->scr, aq, QSPI_SCR);  in atmel_qspi_resume()
694 		.compatible = "atmel,sama5d2-qspi",
698 		.compatible = "microchip,sam9x60-qspi",