Lines Matching +full:num +full:- +full:ports
1 // SPDX-License-Identifier: GPL-2.0
79 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
80 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
81 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
82 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
83 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
84 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
85 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
179 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
199 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
219 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
226 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
255 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_rd_fifo_avail()
263 } while (fifo_retry_count--); in swrm_wait_for_rd_fifo_avail()
266 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
267 return -EIO; in swrm_wait_for_rd_fifo_avail()
280 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_wr_fifo_avail()
284 if (fifo_outstanding_cmds < swrm->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
288 } while (fifo_retry_count--); in swrm_wait_for_wr_fifo_avail()
290 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
291 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
292 return -EIO; in swrm_wait_for_wr_fifo_avail()
311 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
319 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); in qcom_swrm_cmd_fifo_wr_cmd()
322 if (swrm->version <= 0x01030000) in qcom_swrm_cmd_fifo_wr_cmd()
330 ret = wait_for_completion_timeout(&swrm->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
349 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
353 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); in qcom_swrm_cmd_fifo_rd_cmd()
361 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
365 if (cmd_id != swrm->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
366 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { in qcom_swrm_cmd_fifo_rd_cmd()
369 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
371 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); in qcom_swrm_cmd_fifo_rd_cmd()
380 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
382 reg_addr, swrm->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
392 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
398 ctrl->status[dev_num] = status; in qcom_swrm_get_alert_slave_dev_num()
403 return -EINVAL; in qcom_swrm_get_alert_slave_dev_num()
411 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
412 ctrl->slave_status = val; in qcom_swrm_get_device_status()
419 ctrl->status[i] = s; in qcom_swrm_get_device_status()
429 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
435 slave->dev_num = devnum; in qcom_swrm_set_slave_dev_num()
436 mutex_lock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
437 set_bit(devnum, bus->assigned); in qcom_swrm_set_slave_dev_num()
438 mutex_unlock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
454 /*SCP_Devid5 - Devid 4*/ in qcom_swrm_enumerate()
455 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
457 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
458 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
470 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { in qcom_swrm_enumerate()
484 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
496 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); in qcom_swrm_irq_handler()
497 intr_sts_masked = intr_sts & swrm->intr_mask; in qcom_swrm_irq_handler()
509 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
512 sdw_handle_slave_status(&swrm->bus, swrm->status); in qcom_swrm_irq_handler()
518 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n", in qcom_swrm_irq_handler()
520 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
521 if (swrm->slave_status == slave_status) { in qcom_swrm_irq_handler()
522 dev_err(swrm->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
526 qcom_swrm_enumerate(&swrm->bus); in qcom_swrm_irq_handler()
527 sdw_handle_slave_status(&swrm->bus, swrm->status); in qcom_swrm_irq_handler()
531 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
534 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
535 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
538 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
539 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
544 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
545 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
550 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
551 dev_err(swrm->dev, in qcom_swrm_irq_handler()
554 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
557 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
558 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
561 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
564 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
567 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
568 swrm->reg_write(swrm, in qcom_swrm_irq_handler()
569 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
572 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
575 swrm->intr_mask &= in qcom_swrm_irq_handler()
577 swrm->reg_write(swrm, in qcom_swrm_irq_handler()
578 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
581 complete(&swrm->broadcast); in qcom_swrm_irq_handler()
590 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
597 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); in qcom_swrm_irq_handler()
598 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); in qcom_swrm_irq_handler()
599 intr_sts_masked = intr_sts & swrm->intr_mask; in qcom_swrm_irq_handler()
610 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
611 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
613 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
616 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
618 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
620 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, in qcom_swrm_init()
624 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
626 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
628 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
630 if (ctrl->version > 0x01050001) { in qcom_swrm_init()
632 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
636 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
641 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
646 if (ctrl->mmio) { in qcom_swrm_init()
647 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, in qcom_swrm_init()
650 ctrl->slave_status = 0; in qcom_swrm_init()
651 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
652 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
653 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
664 if (msg->flags == SDW_MSG_FLAG_READ) { in qcom_swrm_xfer_msg()
665 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
666 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) in qcom_swrm_xfer_msg()
667 len = msg->len - i; in qcom_swrm_xfer_msg()
671 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
672 msg->addr + i, len, in qcom_swrm_xfer_msg()
673 &msg->buf[i]); in qcom_swrm_xfer_msg()
679 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { in qcom_swrm_xfer_msg()
680 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
681 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
682 msg->dev_num, in qcom_swrm_xfer_msg()
683 msg->addr + i); in qcom_swrm_xfer_msg()
694 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); in qcom_swrm_pre_bank_switch()
698 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
700 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
701 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
703 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
712 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
713 p_params->bps - 1); in qcom_swrm_port_params()
724 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); in qcom_swrm_transport_params()
727 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
729 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; in qcom_swrm_transport_params()
730 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; in qcom_swrm_transport_params()
731 value |= pcfg->si; in qcom_swrm_transport_params()
733 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
737 if (pcfg->lane_control != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
738 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
739 value = pcfg->lane_control; in qcom_swrm_transport_params()
740 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
745 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
746 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
747 value = pcfg->blk_group_count; in qcom_swrm_transport_params()
748 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
753 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
754 && pcfg->hstop != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
755 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
756 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
757 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
759 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
761 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
767 if (pcfg->bp_mode != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
768 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); in qcom_swrm_transport_params()
769 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
780 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); in qcom_swrm_port_enable()
784 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
786 if (enable_ch->enable) in qcom_swrm_port_enable()
787 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
791 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
816 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in qcom_swrm_compute_params()
817 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in qcom_swrm_compute_params()
818 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
819 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
820 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
821 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
822 p_rt->num, pcfg->word_length + 1, in qcom_swrm_compute_params()
829 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_compute_params()
830 slave = s_rt->slave; in qcom_swrm_compute_params()
831 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_compute_params()
832 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_compute_params()
833 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
835 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
837 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
838 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
839 p_rt->transport_params.sample_interval = in qcom_swrm_compute_params()
840 pcfg->si + 1; in qcom_swrm_compute_params()
841 p_rt->transport_params.offset1 = pcfg->off1; in qcom_swrm_compute_params()
842 p_rt->transport_params.offset2 = pcfg->off2; in qcom_swrm_compute_params()
843 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; in qcom_swrm_compute_params()
844 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; in qcom_swrm_compute_params()
846 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
847 p_rt->transport_params.hstop = pcfg->hstop; in qcom_swrm_compute_params()
848 p_rt->transport_params.lane_ctrl = pcfg->lane_control; in qcom_swrm_compute_params()
849 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
850 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
851 p_rt->num, in qcom_swrm_compute_params()
852 pcfg->word_length + 1, in qcom_swrm_compute_params()
875 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
877 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_free_ports()
878 if (m_rt->direction == SDW_DATA_DIR_RX) in qcom_swrm_stream_free_ports()
879 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_free_ports()
881 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_free_ports()
883 list_for_each_entry(p_rt, &m_rt->port_list, port_node) in qcom_swrm_stream_free_ports()
884 clear_bit(p_rt->num, port_mask); in qcom_swrm_stream_free_ports()
887 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
905 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
906 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_alloc_ports()
907 if (m_rt->direction == SDW_DATA_DIR_RX) { in qcom_swrm_stream_alloc_ports()
908 maxport = ctrl->num_dout_ports; in qcom_swrm_stream_alloc_ports()
909 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_alloc_ports()
911 maxport = ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
912 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_alloc_ports()
915 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_stream_alloc_ports()
916 slave = s_rt->slave; in qcom_swrm_stream_alloc_ports()
917 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_stream_alloc_ports()
918 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_stream_alloc_ports()
919 /* Port numbers start from 1 - 14*/ in qcom_swrm_stream_alloc_ports()
926 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
927 ret = -EBUSY; in qcom_swrm_stream_alloc_ports()
931 pconfig[nports].num = pn; in qcom_swrm_stream_alloc_ports()
932 pconfig[nports].ch_mask = p_rt->ch_mask; in qcom_swrm_stream_alloc_ports()
946 sconfig.type = stream->type; in qcom_swrm_stream_alloc_ports()
948 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
953 clear_bit(pconfig[i].num, port_mask); in qcom_swrm_stream_alloc_ports()
956 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
965 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params()
966 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
970 substream->stream); in qcom_swrm_hw_params()
980 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free()
981 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
984 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
992 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream()
994 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1001 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream()
1003 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1009 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup()
1010 struct snd_soc_pcm_runtime *rtd = substream->private_data; in qcom_swrm_startup()
1015 sruntime = sdw_alloc_stream(dai->name); in qcom_swrm_startup()
1017 return -ENOMEM; in qcom_swrm_startup()
1019 ctrl->sruntime[dai->id] = sruntime; in qcom_swrm_startup()
1023 substream->stream); in qcom_swrm_startup()
1024 if (ret < 0 && ret != -ENOTSUPP) { in qcom_swrm_startup()
1025 dev_err(dai->dev, "Failed to set sdw stream on %s\n", in qcom_swrm_startup()
1026 codec_dai->name); in qcom_swrm_startup()
1038 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown()
1040 sdw_release_stream(ctrl->sruntime[dai->id]); in qcom_swrm_shutdown()
1041 ctrl->sruntime[dai->id] = NULL; in qcom_swrm_shutdown()
1059 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1062 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1068 return -ENOMEM; in qcom_swrm_register_dais()
1073 return -ENOMEM; in qcom_swrm_register_dais()
1075 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1080 stream->channels_min = 1; in qcom_swrm_register_dais()
1081 stream->channels_max = 1; in qcom_swrm_register_dais()
1082 stream->rates = SNDRV_PCM_RATE_48000; in qcom_swrm_register_dais()
1083 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; in qcom_swrm_register_dais()
1089 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1096 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1108 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1110 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1111 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1113 ret = of_property_read_u32(np, "qcom,din-ports", &val); in qcom_swrm_get_port_config()
1117 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1118 return -EINVAL; in qcom_swrm_get_port_config()
1120 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1122 ret = of_property_read_u32(np, "qcom,dout-ports", &val); in qcom_swrm_get_port_config()
1126 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1127 return -EINVAL; in qcom_swrm_get_port_config()
1129 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1131 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1132 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1133 set_bit(0, &ctrl->dout_port_mask); in qcom_swrm_get_port_config()
1134 set_bit(0, &ctrl->din_port_mask); in qcom_swrm_get_port_config()
1136 ret = of_property_read_u8_array(np, "qcom,ports-offset1", in qcom_swrm_get_port_config()
1141 ret = of_property_read_u8_array(np, "qcom,ports-offset2", in qcom_swrm_get_port_config()
1146 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", in qcom_swrm_get_port_config()
1151 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", in qcom_swrm_get_port_config()
1156 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &version); in qcom_swrm_get_port_config()
1165 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1168 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); in qcom_swrm_get_port_config()
1171 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); in qcom_swrm_get_port_config()
1174 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); in qcom_swrm_get_port_config()
1177 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); in qcom_swrm_get_port_config()
1180 /* Valid port number range is from 1-14 */ in qcom_swrm_get_port_config()
1181 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1182 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1183 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1184 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1185 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1186 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1187 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1188 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1189 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1197 struct device *dev = &pdev->dev;
1207 return -ENOMEM;
1210 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1211 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1213 if (dev->parent->bus == &slimbus_bus) {
1217 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1218 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1219 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1220 if (!ctrl->regmap)
1221 return -EINVAL;
1223 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1224 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1225 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1226 if (IS_ERR(ctrl->mmio))
1227 return PTR_ERR(ctrl->mmio);
1230 ctrl->irq = of_irq_get(dev->of_node, 0);
1231 if (ctrl->irq < 0) {
1232 ret = ctrl->irq;
1236 ctrl->hclk = devm_clk_get(dev, "iface");
1237 if (IS_ERR(ctrl->hclk)) {
1238 ret = PTR_ERR(ctrl->hclk);
1242 clk_prepare_enable(ctrl->hclk);
1244 ctrl->dev = dev;
1245 dev_set_drvdata(&pdev->dev, ctrl);
1246 mutex_init(&ctrl->port_lock);
1247 init_completion(&ctrl->broadcast);
1248 init_completion(&ctrl->enumeration);
1250 ctrl->bus.ops = &qcom_swrm_ops;
1251 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1252 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1258 params = &ctrl->bus.params;
1259 params->max_dr_freq = DEFAULT_CLK_FREQ;
1260 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1261 params->col = data->default_cols;
1262 params->row = data->default_rows;
1263 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1264 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1265 params->next_bank = !params->curr_bank;
1267 prop = &ctrl->bus.prop;
1268 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1269 prop->num_clk_gears = 0;
1270 prop->num_clk_freq = MAX_FREQ_NUM;
1271 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1272 prop->default_col = data->default_cols;
1273 prop->default_row = data->default_rows;
1275 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1277 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1287 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1295 wait_for_completion_timeout(&ctrl->enumeration,
1302 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1303 ctrl->version & 0xffff);
1308 sdw_bus_master_delete(&ctrl->bus);
1310 clk_disable_unprepare(ctrl->hclk);
1317 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1319 sdw_bus_master_delete(&ctrl->bus);
1320 clk_disable_unprepare(ctrl->hclk);
1326 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1327 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1337 .name = "qcom-soundwire",