88 #define OMAP_PRM_HAS_RSTCTRL	BIT(0)
139 	{ .rst = 0, .st = 0 },
144 	{ .rst = 0, .st = 0 },
150 	{ .rst = 0, .st = 0 },
158 		.name = "mpu", .base = 0x4a306300,
159 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
162 		.name = "tesla", .base = 0x4a306400,
163 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
164 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
167 		.name = "abe", .base = 0x4a306500,
168 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
171 		.name = "always_on_core", .base = 0x4a306600,
172 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
175 		.name = "core", .base = 0x4a306700,
176 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
177 		.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
182 		.name = "ivahd", .base = 0x4a306f00,
183 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
184 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
187 		.name = "cam", .base = 0x4a307000,
188 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
191 		.name = "dss", .base = 0x4a307100,
192 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
195 		.name = "gfx", .base = 0x4a307200,
196 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
199 		.name = "l3init", .base = 0x4a307300,
200 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
203 		.name = "l4per", .base = 0x4a307400,
204 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
208 		.name = "cefuse", .base = 0x4a307600,
209 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
212 		.name = "wkup", .base = 0x4a307700,
213 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
216 		.name = "emu", .base = 0x4a307900,
217 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
220 		.name = "device", .base = 0x4a307b00,
221 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
229 		.name = "mpu", .base = 0x4ae06300,
230 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
233 		.name = "dsp", .base = 0x4ae06400,
234 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
235 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
238 		.name = "abe", .base = 0x4ae06500,
239 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
242 		.name = "coreaon", .base = 0x4ae06600,
243 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
246 		.name = "core", .base = 0x4ae06700,
247 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
248 		.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu",
252 		.name = "iva", .base = 0x4ae07200,
253 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
254 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
257 		.name = "cam", .base = 0x4ae07300,
258 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
261 		.name = "dss", .base = 0x4ae07400,
262 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
265 		.name = "gpu", .base = 0x4ae07500,
266 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
269 		.name = "l3init", .base = 0x4ae07600,
270 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
273 		.name = "custefuse", .base = 0x4ae07700,
274 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
277 		.name = "wkupaon", .base = 0x4ae07800,
278 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
281 		.name = "emu", .base = 0x4ae07a00,
282 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
285 		.name = "device", .base = 0x4ae07c00,
286 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
294 		.name = "mpu", .base = 0x4ae06300,
295 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
298 		.name = "dsp1", .base = 0x4ae06400,
299 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
300 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
303 		.name = "ipu", .base = 0x4ae06500,
304 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
305 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
309 		.name = "coreaon", .base = 0x4ae06628,
310 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
313 		.name = "core", .base = 0x4ae06700,
314 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
315 		.rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
319 		.name = "iva", .base = 0x4ae06f00,
320 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
321 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
324 		.name = "cam", .base = 0x4ae07000,
325 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
328 		.name = "dss", .base = 0x4ae07100,
329 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
332 		.name = "gpu", .base = 0x4ae07200,
333 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
336 		.name = "l3init", .base = 0x4ae07300,
337 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
338 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
342 		.name = "l4per", .base = 0x4ae07400,
343 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
346 		.name = "custefuse", .base = 0x4ae07600,
347 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
350 		.name = "wkupaon", .base = 0x4ae07724,
351 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
354 		.name = "emu", .base = 0x4ae07900,
355 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
358 		.name = "dsp2", .base = 0x4ae07b00,
359 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
360 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
363 		.name = "eve1", .base = 0x4ae07b40,
364 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
365 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
368 		.name = "eve2", .base = 0x4ae07b80,
369 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
370 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
373 		.name = "eve3", .base = 0x4ae07bc0,
374 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
375 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
378 		.name = "eve4", .base = 0x4ae07c00,
379 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
380 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
383 		.name = "rtc", .base = 0x4ae07c60,
384 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
387 		.name = "vpe", .base = 0x4ae07c80,
388 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
405 		.name = "per", .base = 0x44e00c00,
406 		.pwrstctrl = 0xc, .pwrstst = 0x8, .dmap = &omap_prm_noinact,
407 		.rstctrl = 0x0, .rstmap = am3_per_rst_map,
411 		.name = "wkup", .base = 0x44e00d00,
412 		.pwrstctrl = 0x4, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
413 		.rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map,
417 		.name = "mpu", .base = 0x44e00e00,
418 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
421 		.name = "device", .base = 0x44e00f00,
422 		.rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01,
426 		.name = "rtc", .base = 0x44e01000,
427 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
430 		.name = "gfx", .base = 0x44e01100,
431 		.pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact,
432 		.rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
435 		.name = "cefuse", .base = 0x44e01200,
436 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
442 	{ .rst = 1, .st = 0 },
447 	{ .rst = 0, .st = 1 },
448 	{ .rst = 1, .st = 0 },
454 		.name = "mpu", .base = 0x44df0300,
455 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
458 		.name = "gfx", .base = 0x44df0400,
459 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
460 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
463 		.name = "rtc", .base = 0x44df0500,
464 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
467 		.name = "tamper", .base = 0x44df0600,
468 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
471 		.name = "cefuse", .base = 0x44df0700,
472 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
475 		.name = "per", .base = 0x44df0800,
476 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
477 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map,
481 		.name = "wkup", .base = 0x44df2000,
482 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
483 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map,
487 		.name = "device", .base = 0x44df4000,
488 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map,
527 		return 0;  in omap_prm_domain_power_on()
571 		return 0;  in omap_prm_domain_power_off()
600 	return 0;  in omap_prm_domain_power_off()
615 		return 0;  in omap_prm_domain_attach_clock()
618 		return 0;  in omap_prm_domain_attach_clock()
625 	if (error < 0) {  in omap_prm_domain_attach_clock()
632 	return 0;  in omap_prm_domain_attach_clock()
648 					 "#power-domain-cells", 0, &pd_args);  in omap_prm_domain_attach_dev()
649 	if (ret < 0)  in omap_prm_domain_attach_dev()
652 	if (pd_args.args_count != 0)  in omap_prm_domain_attach_dev()
663 	return 0;  in omap_prm_domain_attach_dev()
688 		return 0;  in omap_prm_domain_init()
736 	while (map->rst >= 0) {  in omap_reset_get_st_bit()
766 	 * completed successfully so we can return 0 here (reset deasserted)  in omap_reset_status()
789 	return 0;  in omap_reset_assert()
801 	int ret = 0;  in omap_reset_deassert()
805 		return 0;  in omap_reset_deassert()
865 	if (!_is_valid_reset(reset, reset_spec->args[0]))  in omap_prm_reset_xlate()
868 	return reset_spec->args[0];  in omap_prm_reset_xlate()
886 		return 0;  in omap_prm_reset_init()
921 	while (map->rst >= 0) {  in omap_prm_reset_init()
947 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in omap_prm_probe()
981 	return 0;  in omap_prm_probe()