470 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,  in tegra_pmc_writel()  function
503 		tegra_pmc_writel(pmc, value, offset);  in tegra_pmc_scratch_writel()
562 		tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);  in tegra20_powergate_set()
589 	tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);  in tegra114_powergate_set()
647 			tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);  in __tegra_powergate_remove_clamping()
663 	tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);  in __tegra_powergate_remove_clamping()
1091 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra_pmc_restart_notify()
1541 		tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);  in tegra_io_pad_prepare()
1546 		tegra_pmc_writel(pmc, value, SEL_DPD_TIM);  in tegra_io_pad_prepare()
1573 		tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);  in tegra_io_pad_unprepare()
1596 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);  in tegra_io_pad_power_enable()
1632 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);  in tegra_io_pad_power_disable()
1687 		tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);  in tegra_io_pad_set_voltage()
1692 		tegra_pmc_writel(pmc, value, PMC_PWR_DET);  in tegra_io_pad_set_voltage()
1702 		tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);  in tegra_io_pad_set_voltage()
1797 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);  in tegra_pmc_enter_suspend_mode()
1801 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);  in tegra_pmc_enter_suspend_mode()
1806 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
1931 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
1935 	tegra_pmc_writel(pmc, value, PMC_SCRATCH54);  in tegra_pmc_init_tsense_reset()
1953 	tegra_pmc_writel(pmc, value, PMC_SCRATCH55);  in tegra_pmc_init_tsense_reset()
1957 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
2266 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);  in tegra210_pmc_irq_set_wake()
2267 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);  in tegra210_pmc_irq_set_wake()
2269 	tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);  in tegra210_pmc_irq_set_wake()
2270 	tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);  in tegra210_pmc_irq_set_wake()
2285 	tegra_pmc_writel(pmc, value, offset);  in tegra210_pmc_irq_set_wake()
2325 	tegra_pmc_writel(pmc, value, offset);  in tegra210_pmc_irq_set_type()
2502 	tegra_pmc_writel(pmc, val, clk->offs);  in pmc_clk_mux_set_parent()
2524 	tegra_pmc_writel(pmc, val, offs);  in pmc_clk_set_state()
2687 		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);  in tegra_pmc_clock_register()
2756 	tegra_pmc_writel(pmc, value, offset);  in tegra_pmc_regmap_writel()
2946 	tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);  in tegra_pmc_suspend()
2955 	tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);  in tegra_pmc_resume()
2994 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
3009 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
3014 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
3021 		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),  in tegra20_pmc_init()
3023 		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);  in tegra20_pmc_init()
3040 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_setup_irq_polarity()