Lines Matching +full:ao +full:- +full:secure
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
55 #include <dt-bindings/gpio/tegra186-gpio.h>
56 #include <dt-bindings/gpio/tegra194-gpio.h>
57 #include <dt-bindings/soc/tegra-pmc.h>
186 /* for secure PMC */
366 * struct tegra_pmc - NVIDIA Tegra PMC
383 * @corereq_high: core power request is active-high
384 * @sysclkreq_high: system clock request is active-high
452 if (pmc->tz_only) { in tegra_pmc_readl()
456 if (pmc->dev) in tegra_pmc_readl()
457 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
467 return readl(pmc->base + offset); in tegra_pmc_readl()
475 if (pmc->tz_only) { in tegra_pmc_writel()
479 if (pmc->dev) in tegra_pmc_writel()
480 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
487 writel(value, pmc->base + offset); in tegra_pmc_writel()
493 if (pmc->tz_only) in tegra_pmc_scratch_readl()
496 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
502 if (pmc->tz_only) in tegra_pmc_scratch_writel()
505 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
515 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
523 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
528 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
535 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
536 return -EINVAL; in tegra_powergate_lookup()
538 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
542 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
546 return -ENODEV; in tegra_powergate_lookup()
558 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
559 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
567 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
607 * tegra_powergate_set() - set the state of a partition
617 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
618 return -EINVAL; in tegra_powergate_set()
620 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
623 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
627 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
629 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
639 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
646 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
666 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
677 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
678 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); in tegra_powergate_prepare_clocks()
680 if (!pg->clk_rates[i]) { in tegra_powergate_prepare_clocks()
681 err = -EINVAL; in tegra_powergate_prepare_clocks()
685 if (pg->clk_rates[i] <= safe_rate) in tegra_powergate_prepare_clocks()
694 err = clk_set_rate(pg->clks[i], safe_rate); in tegra_powergate_prepare_clocks()
702 while (i--) in tegra_powergate_prepare_clocks()
703 clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_prepare_clocks()
713 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
714 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_unprepare_clocks()
726 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
727 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
735 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
736 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
744 while (i--) in tegra_powergate_enable_clocks()
745 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
755 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
761 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
777 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
783 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
789 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
790 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
811 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
830 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
840 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
853 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
868 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
874 pg->genpd.name, err); in tegra_genpd_power_on()
878 reset_control_release(pg->reset); in tegra_genpd_power_on()
887 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
890 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
893 pg->genpd.name, err); in tegra_genpd_power_off()
900 pg->genpd.name, err); in tegra_genpd_power_off()
901 reset_control_release(pg->reset); in tegra_genpd_power_off()
908 * tegra_powergate_power_on() - power on partition
914 return -EINVAL; in tegra_powergate_power_on()
921 * tegra_powergate_power_off() - power off partition
927 return -EINVAL; in tegra_powergate_power_off()
934 * tegra_powergate_is_powered() - check if partition is powered
941 return -EINVAL; in tegra_powergate_is_powered()
947 * tegra_powergate_remove_clamping() - remove power clamps for partition
953 return -EINVAL; in tegra_powergate_remove_clamping()
960 * tegra_powergate_sequence_power_up() - power up partition
974 return -EINVAL; in tegra_powergate_sequence_power_up()
978 return -ENOMEM; in tegra_powergate_sequence_power_up()
980 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_sequence_power_up()
981 if (!pg->clk_rates) { in tegra_powergate_sequence_power_up()
982 kfree(pg->clks); in tegra_powergate_sequence_power_up()
983 return -ENOMEM; in tegra_powergate_sequence_power_up()
986 pg->id = id; in tegra_powergate_sequence_power_up()
987 pg->clks = &clk; in tegra_powergate_sequence_power_up()
988 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
989 pg->reset = rst; in tegra_powergate_sequence_power_up()
990 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
994 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
997 kfree(pg->clk_rates); in tegra_powergate_sequence_power_up()
1005 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1015 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1016 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1018 return -EINVAL; in tegra_get_cpu_powergate_id()
1022 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1037 * tegra_pmc_cpu_power_on() - power on CPU partition
1052 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1072 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
1082 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
1086 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
1107 seq_printf(s, "------------------\n"); in powergate_show()
1109 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1114 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1125 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
1127 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
1128 return -ENOMEM; in tegra_powergate_debugfs_init()
1142 return -ENODEV; in tegra_powergate_of_get_clks()
1144 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1145 if (!pg->clks) in tegra_powergate_of_get_clks()
1146 return -ENOMEM; in tegra_powergate_of_get_clks()
1148 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_of_get_clks()
1149 if (!pg->clk_rates) { in tegra_powergate_of_get_clks()
1150 kfree(pg->clks); in tegra_powergate_of_get_clks()
1151 return -ENOMEM; in tegra_powergate_of_get_clks()
1155 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1156 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1157 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1162 pg->num_clks = count; in tegra_powergate_of_get_clks()
1167 while (i--) in tegra_powergate_of_get_clks()
1168 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1170 kfree(pg->clk_rates); in tegra_powergate_of_get_clks()
1171 kfree(pg->clks); in tegra_powergate_of_get_clks()
1179 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1182 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1183 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1184 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1189 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1196 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1198 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1202 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1207 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1208 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1216 struct device *dev = pmc->dev; in tegra_powergate_add()
1223 return -ENOMEM; in tegra_powergate_add()
1225 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1228 err = -ENODEV; in tegra_powergate_add()
1236 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1238 pg->id = id; in tegra_powergate_add()
1239 pg->genpd.name = np->name; in tegra_powergate_add()
1240 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1241 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1242 pg->pmc = pmc; in tegra_powergate_add()
1244 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1265 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1272 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1279 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1284 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1287 reset_control_put(pg->reset); in tegra_powergate_add()
1290 while (pg->num_clks--) in tegra_powergate_add()
1291 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1293 kfree(pg->clks); in tegra_powergate_add()
1296 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1306 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1316 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); in tegra_pmc_core_pd_set_performance_state()
1318 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", in tegra_pmc_core_pd_set_performance_state()
1323 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1324 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1325 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1330 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", in tegra_pmc_core_pd_set_performance_state()
1351 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1353 return -ENOMEM; in tegra_pmc_core_pd_add()
1355 genpd->name = np->name; in tegra_pmc_core_pd_add()
1356 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; in tegra_pmc_core_pd_add()
1357 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; in tegra_pmc_core_pd_add()
1359 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1); in tegra_pmc_core_pd_add()
1361 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1366 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1372 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1376 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1397 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_init()
1416 if (of_parse_phandle_with_args(child, "power-domains", in tegra_powergate_init()
1417 "#power-domain-cells", in tegra_powergate_init()
1441 reset_control_put(pg->reset); in tegra_powergate_remove()
1443 while (pg->num_clks--) in tegra_powergate_remove()
1444 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1446 kfree(pg->clks); in tegra_powergate_remove()
1448 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1474 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_remove_all()
1486 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1487 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1488 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1503 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1504 return -ENOENT; in tegra_io_pad_get_dpd_register_bit()
1507 if (pad->dpd == UINT_MAX) in tegra_io_pad_get_dpd_register_bit()
1508 return -ENOTSUPP; in tegra_io_pad_get_dpd_register_bit()
1510 *mask = BIT(pad->dpd % 32); in tegra_io_pad_get_dpd_register_bit()
1512 if (pad->dpd < 32) { in tegra_io_pad_get_dpd_register_bit()
1513 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1514 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1516 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1517 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1534 if (pmc->clk) { in tegra_io_pad_prepare()
1535 rate = pmc->rate; in tegra_io_pad_prepare()
1537 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1538 return -ENODEV; in tegra_io_pad_prepare()
1567 return -ETIMEDOUT; in tegra_io_pad_poll()
1572 if (pmc->clk) in tegra_io_pad_unprepare()
1577 * tegra_io_pad_power_enable() - enable power to I/O pad
1588 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1592 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1600 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1607 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1613 * tegra_io_pad_power_disable() - disable power to I/O pad
1624 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1628 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1636 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1643 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1672 return -ENOENT; in tegra_io_pad_set_voltage()
1674 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1675 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1677 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1679 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1683 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1685 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1689 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1691 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1698 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1700 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1705 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1719 return -ENOENT; in tegra_io_pad_get_voltage()
1721 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1722 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1724 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1729 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1736 * tegra_io_rail_power_on() - enable power to I/O rail
1748 * tegra_io_rail_power_off() - disable power to I/O rail
1762 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1770 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1785 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1795 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1799 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1814 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1815 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1819 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1823 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1827 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1831 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1836 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1838 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1839 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1841 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1843 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1844 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1846 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1848 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1850 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1852 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1853 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1855 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1856 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1858 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1860 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1861 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1863 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1864 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1866 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1867 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1869 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1870 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1872 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1874 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1875 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1877 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1878 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1885 if (pmc->soc->init) in tegra_pmc_init()
1886 pmc->soc->init(pmc); in tegra_pmc_init()
1893 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1897 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1900 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1902 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1906 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1911 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1912 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1916 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1917 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1921 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1922 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1926 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1949 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1959 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1969 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
1977 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
1987 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2012 return -EINVAL; in tegra_io_pad_pinconf_get()
2016 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2024 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2032 return -EINVAL; in tegra_io_pad_pinconf_get()
2053 return -EINVAL; in tegra_io_pad_pinconf_set()
2062 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
2064 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
2071 return -EINVAL; in tegra_io_pad_pinconf_set()
2072 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2077 return -EINVAL; in tegra_io_pad_pinconf_set()
2099 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2102 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2103 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2104 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2106 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2108 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2109 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2110 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2123 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2124 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2125 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2127 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2130 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2140 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2141 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2142 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2144 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2147 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2154 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2157 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2165 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2179 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
2180 return -EINVAL; in tegra_pmc_irq_translate()
2182 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2183 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
2191 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
2192 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2198 return -EINVAL; in tegra_pmc_irq_alloc()
2200 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2201 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
2203 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
2206 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2210 event->id, in tegra_pmc_irq_alloc()
2211 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2215 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2218 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
2219 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2227 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2228 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2229 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2233 event->id, in tegra_pmc_irq_alloc()
2234 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2237 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2238 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2244 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2245 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2262 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2263 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2273 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2296 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2297 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2299 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2322 return -EINVAL; in tegra210_pmc_irq_set_type()
2336 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2337 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2340 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2343 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2350 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2353 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2363 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2381 return -EINVAL; in tegra186_pmc_irq_set_type()
2384 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2391 if (data->parent_data) in tegra_irq_mask_parent()
2397 if (data->parent_data) in tegra_irq_unmask_parent()
2403 if (data->parent_data) in tegra_irq_eoi_parent()
2411 if (data->parent_data) in tegra_irq_set_affinity_parent()
2414 return -EINVAL; in tegra_irq_set_affinity_parent()
2422 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2431 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2432 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2433 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2434 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2435 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2436 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2437 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2439 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2441 if (!pmc->domain) { in tegra_pmc_irq_init()
2442 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2443 return -ENOMEM; in tegra_pmc_irq_init()
2457 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2461 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2465 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2470 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2488 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2499 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2500 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2501 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2502 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2503 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2513 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2532 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2541 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2561 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2563 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2565 init.name = data->name; in tegra_pmc_clk_out_register()
2567 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2568 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2572 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2573 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2574 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2575 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2577 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2584 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2591 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2600 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2617 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2619 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2627 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2628 gate->offs = offset; in tegra_pmc_clk_gate_register()
2629 gate->shift = shift; in tegra_pmc_clk_gate_register()
2631 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2642 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2643 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2649 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2653 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2654 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2655 if (!clk_data->clks) in tegra_pmc_clock_register()
2658 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2661 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2663 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2666 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2670 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2671 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2675 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2677 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2679 data->name, err); in tegra_pmc_clock_register()
2683 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2686 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2694 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2705 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2713 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2719 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2724 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2777 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2778 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2781 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2791 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2805 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2806 return -ENODEV; in tegra_pmc_probe()
2808 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2812 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, in tegra_pmc_probe()
2819 base = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2825 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2826 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2827 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2829 pmc->wake = base; in tegra_pmc_probe()
2834 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2835 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2836 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2838 pmc->aotag = base; in tegra_pmc_probe()
2843 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2844 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2845 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2847 pmc->scratch = base; in tegra_pmc_probe()
2850 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
2851 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
2852 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
2854 if (err != -ENOENT) { in tegra_pmc_probe()
2855 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); in tegra_pmc_probe()
2859 pmc->clk = NULL; in tegra_pmc_probe()
2867 if (pmc->clk) { in tegra_pmc_probe()
2868 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2869 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2871 dev_err(&pdev->dev, in tegra_pmc_probe()
2876 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2879 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2895 dev_err(&pdev->dev, "unable to register restart handler, %d\n", in tegra_pmc_probe()
2908 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2916 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2917 iounmap(pmc->base); in tegra_pmc_probe()
2918 pmc->base = base; in tegra_pmc_probe()
2919 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
2921 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2928 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
2932 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
2934 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
2935 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
2936 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2998 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3003 if (pmc->corereq_high) in tegra20_pmc_init()
3017 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3018 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3019 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3020 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3251 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3253 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3254 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3255 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3256 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3340 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3349 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3362 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3363 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3364 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3365 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3366 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3370 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3376 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3437 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3438 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3439 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3440 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3441 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3445 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3450 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3451 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3452 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3453 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3465 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3467 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3468 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3470 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3471 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3503 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3505 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3513 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3592 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3593 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3594 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3595 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3596 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3598 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3599 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3603 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3604 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3606 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3607 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3608 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3609 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3610 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3614 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3615 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3616 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3617 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3618 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3619 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3620 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3621 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3623 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3634 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3635 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3637 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3638 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3790 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3791 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3792 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3793 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3794 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3795 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3796 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3797 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3798 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3807 * Older device-trees don't have core PD, and thus, there are in tegra_pmc_sync_state()
3811 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
3814 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
3816 /* this is a no-op if core regulator isn't used */ in tegra_pmc_sync_state()
3817 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
3819 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
3827 .name = "tegra-pmc",
3843 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3850 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3851 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3853 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
3860 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3877 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
3882 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
3883 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
3886 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
3902 * nice with multi-platform kernels. in tegra_pmc_early_init()
3914 return -ENXIO; in tegra_pmc_early_init()
3918 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
3919 if (!pmc->base) { in tegra_pmc_early_init()
3922 return -ENXIO; in tegra_pmc_early_init()
3926 pmc->soc = match->data; in tegra_pmc_early_init()
3928 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
3929 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
3932 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3933 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
3934 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
3938 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
3940 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
3942 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()