Lines Matching +full:0 +full:x7000e400
59 #define PMC_CNTRL 0x0
70 #define PMC_WAKE_MASK 0x0c
71 #define PMC_WAKE_LEVEL 0x10
72 #define PMC_WAKE_STATUS 0x14
73 #define PMC_SW_WAKE_STATUS 0x18
74 #define PMC_DPD_PADS_ORIDE 0x1c
77 #define DPD_SAMPLE 0x020
78 #define DPD_SAMPLE_ENABLE BIT(0)
79 #define DPD_SAMPLE_DISABLE (0 << 0)
81 #define PWRGATE_TOGGLE 0x30
84 #define REMOVE_CLAMPING 0x34
86 #define PWRGATE_STATUS 0x38
88 #define PMC_BLINK_TIMER 0x40
89 #define PMC_IMPL_E_33V_PWR 0x40
91 #define PMC_PWR_DET 0x48
100 #define PMC_CPUPWRGOOD_TIMER 0xc8
101 #define PMC_CPUPWROFF_TIMER 0xcc
102 #define PMC_COREPWRGOOD_TIMER 0x3c
103 #define PMC_COREPWROFF_TIMER 0xe0
105 #define PMC_PWR_DET_VALUE 0xe4
107 #define PMC_USB_DEBOUNCE_DEL 0xec
108 #define PMC_USB_AO 0xf0
110 #define PMC_SCRATCH41 0x140
112 #define PMC_WAKE2_MASK 0x160
113 #define PMC_WAKE2_LEVEL 0x164
114 #define PMC_WAKE2_STATUS 0x168
115 #define PMC_SW_WAKE2_STATUS 0x16c
117 #define PMC_CLK_OUT_CNTRL 0x1a8
118 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
119 #define PMC_SENSOR_CTRL 0x1b0
123 #define PMC_RST_STATUS_POR 0
130 #define IO_DPD_REQ 0x1b8
131 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
136 #define IO_DPD_STATUS 0x1bc
137 #define IO_DPD2_REQ 0x1c0
138 #define IO_DPD2_STATUS 0x1c4
139 #define SEL_DPD_TIM 0x1c8
141 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
142 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
144 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
145 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
146 #define PMC_UTMIP_UHSIC_FAKE 0x218
148 #define PMC_SCRATCH54 0x258
150 #define PMC_SCRATCH54_ADDR_SHIFT 0
152 #define PMC_SCRATCH55 0x25c
158 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
160 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
162 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
163 #define PMC_UTMIP_MASTER_CONFIG 0x274
164 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
165 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
167 #define GPU_RG_CNTRL 0x2d4
169 #define PMC_UTMIP_PAD_CFG0 0x4c0
170 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
171 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
173 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
175 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
176 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
178 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
179 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
181 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
183 #define WAKE_AOWAKE_CTRL 0x4f4
184 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
187 #define TEGRA_SMC_PMC 0xc2fffe00
188 #define TEGRA_SMC_PMC_READ 0xaa
189 #define TEGRA_SMC_PMC_WRITE 0xbb
311 .irq = 0, \
453 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, in tegra_pmc_readl()
454 0, 0, 0, &res); in tegra_pmc_readl()
477 value, 0, 0, 0, 0, &res); in tegra_pmc_writel()
516 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
518 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
538 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
603 return 0; in tegra114_powergate_set()
624 return 0; in tegra_powergate_set()
647 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
668 return 0; in __tegra_powergate_remove_clamping()
677 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
699 return 0; in tegra_powergate_prepare_clocks()
713 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
719 return 0; in tegra_powergate_unprepare_clocks()
726 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
735 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
741 return 0; in tegra_powergate_enable_clocks()
762 if (err < 0) in tegra_powergate_power_up()
801 return 0; in tegra_powergate_power_up()
848 return 0; in tegra_powergate_power_down()
891 if (err < 0) { in tegra_genpd_power_off()
1030 if (id < 0) in tegra_pmc_cpu_is_powered()
1045 if (id < 0) in tegra_pmc_cpu_power_on()
1060 if (id < 0) in tegra_pmc_cpu_remove_clamping()
1076 if (strcmp(cmd, "recovery") == 0) in tegra_pmc_restart_notify()
1079 if (strcmp(cmd, "bootloader") == 0) in tegra_pmc_restart_notify()
1082 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
1109 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1111 if (status < 0) in powergate_show()
1118 return 0; in powergate_show()
1130 return 0; in tegra_powergate_debugfs_init()
1141 if (count == 0) in tegra_powergate_of_get_clks()
1154 for (i = 0; i < count; i++) { in tegra_powergate_of_get_clks()
1164 return 0; in tegra_powergate_of_get_clks()
1190 if (err < 0) { in tegra_powergate_of_get_resets()
1199 if (err < 0) in tegra_powergate_of_get_resets()
1218 int id, err = 0; in tegra_powergate_add()
1226 if (id < 0) { in tegra_powergate_add()
1247 if (err < 0) { in tegra_powergate_add()
1253 if (err < 0) { in tegra_powergate_add()
1266 if (err < 0) { in tegra_powergate_add()
1273 if (err < 0) { in tegra_powergate_add()
1281 return 0; in tegra_powergate_add()
1335 return 0; in tegra_pmc_core_pd_set_performance_state()
1378 return 0; in tegra_pmc_core_pd_add()
1391 int err = 0; in tegra_powergate_init()
1407 return 0; in tegra_powergate_init()
1411 if (err < 0) { in tegra_powergate_init()
1418 0, &parent_args)) in tegra_powergate_init()
1422 child_args.args_count = 0; in tegra_powergate_init()
1486 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1520 return 0; in tegra_io_pad_get_dpd_register_bit()
1549 return 0; in tegra_io_pad_prepare()
1562 return 0; in tegra_io_pad_poll()
1580 * Returns: 0 on success or a negative error code on failure.
1591 if (err < 0) { in tegra_io_pad_power_enable()
1598 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1599 if (err < 0) { in tegra_io_pad_power_enable()
1616 * Returns: 0 on success or a negative error code on failure.
1627 if (err < 0) { in tegra_io_pad_power_disable()
1635 if (err < 0) { in tegra_io_pad_power_disable()
1709 return 0; in tegra_io_pad_set_voltage()
1729 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1775 unsigned long long rate = 0; in tegra_pmc_enter_suspend_mode()
1792 if (WARN_ON_ONCE(rate == 0)) in tegra_pmc_enter_suspend_mode()
1818 case 0: in tegra_pmc_parse_dt()
1852 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1877 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1880 return 0; in tegra_pmc_parse_dt()
1927 pinmux = 0; in tegra_pmc_init_tsense_reset()
1946 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) in tegra_pmc_init_tsense_reset()
1947 + ((value >> 24) & 0xff); in tegra_pmc_init_tsense_reset()
1948 checksum &= 0xff; in tegra_pmc_init_tsense_reset()
1949 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1990 return 0; in tegra_io_pad_pinctrl_get_group_pins()
2017 if (ret < 0) in tegra_io_pad_pinconf_get()
2025 if (ret < 0) in tegra_io_pad_pinconf_get()
2037 return 0; in tegra_io_pad_pinconf_get()
2055 for (i = 0; i < num_configs; ++i) { in tegra_io_pad_pinconf_set()
2081 return 0; in tegra_io_pad_pinconf_set()
2100 return 0; in tegra_pmc_pinctrl_init()
2115 return 0; in tegra_pmc_pinctrl_init()
2155 int err = 0; in tegra_pmc_reset_sysfs_init()
2159 if (err < 0) in tegra_pmc_reset_sysfs_init()
2167 if (err < 0) in tegra_pmc_reset_sysfs_init()
2182 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2185 return 0; in tegra_pmc_irq_translate()
2195 int err = 0; in tegra_pmc_irq_alloc()
2200 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2206 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2212 if (err < 0) in tegra_pmc_irq_alloc()
2217 spec.param[0] = GIC_SPI; in tegra_pmc_irq_alloc()
2228 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2266 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2267 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2269 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2270 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2287 return 0; in tegra210_pmc_irq_set_wake()
2327 return 0; in tegra210_pmc_irq_set_type()
2340 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2355 return 0; in tegra186_pmc_irq_set_wake()
2386 return 0; in tegra186_pmc_irq_set_type()
2429 return 0; in tegra_pmc_irq_init()
2439 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2446 return 0; in tegra_pmc_irq_init()
2505 return 0; in pmc_clk_mux_set_parent()
2515 return val ? 1 : 0; in pmc_clk_is_enabled()
2534 return 0; in pmc_clk_enable()
2541 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2584 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2593 return 0; in pmc_clk_gate_enable()
2600 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2625 init.flags = 0; in tegra_pmc_clk_gate_register()
2660 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) in tegra_pmc_clock_register()
2663 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2687 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2749 return 0; in tegra_pmc_regmap_readl()
2757 return 0; in tegra_pmc_regmap_writel()
2786 return 0; in tegra_pmc_regmap_init()
2809 if (err < 0) in tegra_pmc_probe()
2818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in tegra_pmc_probe()
2889 if (err < 0) in tegra_pmc_probe()
2905 if (err < 0) in tegra_pmc_probe()
2909 if (err < 0) in tegra_pmc_probe()
2913 if (err < 0) in tegra_pmc_probe()
2925 return 0; in tegra_pmc_probe()
2948 return 0; in tegra_pmc_suspend()
2955 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
2957 return 0; in tegra_pmc_resume()
2975 .scratch0 = 0x50,
2976 .dpd_req = 0x1b8,
2977 .dpd_status = 0x1bc,
2978 .dpd2_req = 0x1c0,
2979 .dpd2_status = 0x1c4,
2980 .rst_status = 0x1b4,
2981 .rst_source_shift = 0x0,
2982 .rst_source_mask = 0x7,
2983 .rst_level_shift = 0x0,
2984 .rst_level_mask = 0x0,
3021 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
3046 .num_cpu_powergates = 0,
3053 .num_io_pads = 0,
3055 .num_pin_descs = 0,
3062 .num_reset_sources = 0,
3064 .num_reset_levels = 0,
3066 .num_pmc_clks = 0,
3113 .num_io_pads = 0,
3115 .num_pin_descs = 0,
3124 .num_reset_levels = 0,
3169 .num_io_pads = 0,
3171 .num_pin_descs = 0,
3180 .num_reset_levels = 0,
3240 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3296 .num_reset_levels = 0,
3342 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3423 .num_reset_levels = 0,
3434 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3471 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3482 .scratch0 = 0x2000,
3483 .dpd_req = 0x74,
3484 .dpd_status = 0x78,
3485 .dpd2_req = 0x7c,
3486 .dpd2_status = 0x80,
3487 .rst_status = 0x70,
3488 .rst_source_shift = 0x2,
3489 .rst_source_mask = 0x3c,
3490 .rst_level_shift = 0x0,
3491 .rst_level_mask = 0x3,
3504 if (index < 0) { in tegra186_pmc_setup_irq_polarity()
3553 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3558 .num_powergates = 0,
3560 .num_cpu_powergates = 0,
3583 .num_pmc_clks = 0,
3590 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3638 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3649 .scratch0 = 0x2000,
3650 .dpd_req = 0x74,
3651 .dpd_status = 0x78,
3652 .dpd2_req = 0x7c,
3653 .dpd2_status = 0x80,
3654 .rst_status = 0x70,
3655 .rst_source_shift = 0x2,
3656 .rst_source_mask = 0x7c,
3657 .rst_level_shift = 0x0,
3658 .rst_level_mask = 0x3,
3692 .num_powergates = 0,
3694 .num_cpu_powergates = 0,
3717 .num_pmc_clks = 0,
3723 .scratch0 = 0x2000,
3724 .dpd_req = 0,
3725 .dpd_status = 0,
3726 .dpd2_req = 0,
3727 .dpd2_status = 0,
3728 .rst_status = 0x70,
3729 .rst_source_shift = 0x2,
3730 .rst_source_mask = 0xfc,
3731 .rst_level_shift = 0x0,
3732 .rst_level_mask = 0x3,
3760 .num_powergates = 0,
3762 .num_cpu_powergates = 0,
3769 .num_io_pads = 0,
3771 .num_pin_descs = 0,
3782 .num_wake_events = 0,
3785 .num_pmc_clks = 0,
3844 value = saved ^ 0xffffffff; in tegra_pmc_detect_tz_only()
3846 if (value == 0xffffffff) in tegra_pmc_detect_tz_only()
3847 value = 0xdeadbeef; in tegra_pmc_detect_tz_only()
3854 if (value == 0) { in tegra_pmc_detect_tz_only()
3894 regs.start = 0x7000e400; in tegra_pmc_early_init()
3895 regs.end = 0x7000e7ff; in tegra_pmc_early_init()
3904 return 0; in tegra_pmc_early_init()
3911 if (of_address_to_resource(np, 0, ®s) < 0) { in tegra_pmc_early_init()
3932 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3947 return 0; in tegra_pmc_early_init()