39 	complete(&fuse->apbdma.wait);  in apb_dma_complete()
54 	mutex_lock(&fuse->apbdma.lock);  in tegra20_fuse_read()
56 	fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;  in tegra20_fuse_read()
58 	err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);  in tegra20_fuse_read()
62 	dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,  in tegra20_fuse_read()
63 					       fuse->apbdma.phys,  in tegra20_fuse_read()
72 	reinit_completion(&fuse->apbdma.wait);  in tegra20_fuse_read()
75 	dma_async_issue_pending(fuse->apbdma.chan);  in tegra20_fuse_read()
76 	time_left = wait_for_completion_timeout(&fuse->apbdma.wait,  in tegra20_fuse_read()
80 		dmaengine_terminate_all(fuse->apbdma.chan);  in tegra20_fuse_read()
82 		value = *fuse->apbdma.virt;  in tegra20_fuse_read()
85 	mutex_unlock(&fuse->apbdma.lock);  in tegra20_fuse_read()
94 	return of_device_is_compatible(np, "nvidia,tegra20-apbdma");  in dma_filter()
104 	fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL);  in tegra20_fuse_probe()
105 	if (!fuse->apbdma.chan)  in tegra20_fuse_probe()
108 	fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),  in tegra20_fuse_probe()
109 					       &fuse->apbdma.phys,  in tegra20_fuse_probe()
111 	if (!fuse->apbdma.virt) {  in tegra20_fuse_probe()
112 		dma_release_channel(fuse->apbdma.chan);  in tegra20_fuse_probe()
116 	fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in tegra20_fuse_probe()
117 	fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in tegra20_fuse_probe()
118 	fuse->apbdma.config.src_maxburst = 1;  in tegra20_fuse_probe()
119 	fuse->apbdma.config.dst_maxburst = 1;  in tegra20_fuse_probe()
120 	fuse->apbdma.config.direction = DMA_DEV_TO_MEM;  in tegra20_fuse_probe()
121 	fuse->apbdma.config.device_fc = false;  in tegra20_fuse_probe()
123 	init_completion(&fuse->apbdma.wait);  in tegra20_fuse_probe()
124 	mutex_init(&fuse->apbdma.lock);  in tegra20_fuse_probe()