Lines Matching +full:tegra194 +full:- +full:ccplex
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
38 { .compatible = "nvidia,tegra20-car", },
39 { .compatible = "nvidia,tegra30-car", },
40 { .compatible = "nvidia,tegra114-car", },
41 { .compatible = "nvidia,tegra124-car", },
42 { .compatible = "nvidia,tegra132-car", },
43 { .compatible = "nvidia,tegra210-car", },
54 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
57 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
60 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
63 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
66 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
69 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
72 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
75 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
78 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
91 buffer[i] = fuse->read(fuse, offset + i * 4); in tegra_fuse_read()
98 .name = "tsensor-cpu1",
104 .name = "tsensor-cpu2",
110 .name = "tsensor-cpu0",
116 .name = "xusb-pad-calibration",
122 .name = "tsensor-cpu3",
128 .name = "sata-calibration",
134 .name = "tsensor-gpu",
140 .name = "tsensor-mem0",
146 .name = "tsensor-mem1",
152 .name = "tsensor-pllx",
158 .name = "tsensor-common",
164 .name = "tsensor-realignment",
170 .name = "gpu-calibration",
176 .name = "xusb-pad-calibration-ext",
186 void __iomem *base = fuse->base; in tegra_fuse_probe()
193 fuse->phys = res->start; in tegra_fuse_probe()
194 fuse->base = devm_ioremap_resource(&pdev->dev, res); in tegra_fuse_probe()
195 if (IS_ERR(fuse->base)) { in tegra_fuse_probe()
196 err = PTR_ERR(fuse->base); in tegra_fuse_probe()
197 fuse->base = base; in tegra_fuse_probe()
201 fuse->clk = devm_clk_get(&pdev->dev, "fuse"); in tegra_fuse_probe()
202 if (IS_ERR(fuse->clk)) { in tegra_fuse_probe()
203 if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) in tegra_fuse_probe()
204 dev_err(&pdev->dev, "failed to get FUSE clock: %ld", in tegra_fuse_probe()
205 PTR_ERR(fuse->clk)); in tegra_fuse_probe()
207 fuse->base = base; in tegra_fuse_probe()
208 return PTR_ERR(fuse->clk); in tegra_fuse_probe()
212 fuse->dev = &pdev->dev; in tegra_fuse_probe()
214 pm_runtime_enable(&pdev->dev); in tegra_fuse_probe()
216 if (fuse->soc->probe) { in tegra_fuse_probe()
217 err = fuse->soc->probe(fuse); in tegra_fuse_probe()
223 nvmem.dev = &pdev->dev; in tegra_fuse_probe()
225 nvmem.id = -1; in tegra_fuse_probe()
233 nvmem.size = fuse->soc->info->size; in tegra_fuse_probe()
238 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); in tegra_fuse_probe()
239 if (IS_ERR(fuse->nvmem)) { in tegra_fuse_probe()
240 err = PTR_ERR(fuse->nvmem); in tegra_fuse_probe()
241 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", in tegra_fuse_probe()
252 fuse->clk = NULL; in tegra_fuse_probe()
253 fuse->base = base; in tegra_fuse_probe()
254 pm_runtime_disable(&pdev->dev); in tegra_fuse_probe()
262 err = clk_prepare_enable(fuse->clk); in tegra_fuse_runtime_resume()
273 clk_disable_unprepare(fuse->clk); in tegra_fuse_runtime_suspend()
283 * Critical for RAM re-repair operation, which must occur on resume in tegra_fuse_suspend()
284 * from LP1 system suspend and as part of CCPLEX cluster switching. in tegra_fuse_suspend()
286 if (fuse->soc->clk_suspend_on) in tegra_fuse_suspend()
298 if (fuse->soc->clk_suspend_on) in tegra_fuse_resume()
314 .name = "tegra-fuse",
325 unsigned int offset = fuse->soc->info->spare + spare * 4; in tegra_fuse_read_spare()
327 return fuse->read_early(fuse, offset) & 1; in tegra_fuse_read_spare()
332 return fuse->read_early(fuse, offset); in tegra_fuse_read_early()
337 if (!fuse->read || !fuse->clk) in tegra_fuse_readl()
338 return -EPROBE_DEFER; in tegra_fuse_readl()
340 if (IS_ERR(fuse->clk)) in tegra_fuse_readl()
341 return PTR_ERR(fuse->clk); in tegra_fuse_readl()
343 *value = fuse->read(fuse, offset); in tegra_fuse_readl()
399 * register for Tegra194 devices. A value of 0 indicates that the in platform_show()
400 * platform type is silicon and all other non-zero values indicate in platform_show()
429 attr->family = kasprintf(GFP_KERNEL, "Tegra"); in tegra_soc_device_register()
430 attr->revision = kasprintf(GFP_KERNEL, "%s", in tegra_soc_device_register()
432 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); in tegra_soc_device_register()
433 attr->custom_attr_group = fuse->soc->soc_attr_group; in tegra_soc_device_register()
437 kfree(attr->soc_id); in tegra_soc_device_register()
438 kfree(attr->revision); in tegra_soc_device_register()
439 kfree(attr->family); in tegra_soc_device_register()
458 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_init_fuse()
459 * 64-bit ARM device tree files for Tegra are required to have in tegra_init_fuse()
462 * This is for backwards-compatibility with old device trees in tegra_init_fuse()
475 fuse->soc = &tegra20_fuse_soc; in tegra_init_fuse()
481 fuse->soc = &tegra30_fuse_soc; in tegra_init_fuse()
487 fuse->soc = &tegra114_fuse_soc; in tegra_init_fuse()
493 fuse->soc = &tegra124_fuse_soc; in tegra_init_fuse()
504 * nice with multi-platform kernels. in tegra_init_fuse()
515 return -ENXIO; in tegra_init_fuse()
518 fuse->soc = match->data; in tegra_init_fuse()
529 return -ENXIO; in tegra_init_fuse()
533 fuse->base = ioremap(regs.start, resource_size(®s)); in tegra_init_fuse()
534 if (!fuse->base) { in tegra_init_fuse()
536 return -ENXIO; in tegra_init_fuse()
539 fuse->soc->init(fuse); in tegra_init_fuse()
548 if (fuse->soc->lookups) { in tegra_init_fuse()
549 size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; in tegra_init_fuse()
551 fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); in tegra_init_fuse()
552 if (fuse->lookups) in tegra_init_fuse()
553 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); in tegra_init_fuse()