Lines Matching +full:geni +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
7 #include <linux/dma-mapping.h>
14 #include <linux/qcom-geni-se.h>
19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
22 * like UART, SPI, I2C, I3C, etc.
28 * GENI based QUP is a highly-flexible and programmable module for supporting
29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
34 * of a DMA Engine and GENI sub modules which enable serial engines to
38 * +-----------------------------------------+
40 * | +----------------------------+ |
41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
43 * <---Clock Perf.----+ +----+-----------------------+ | |
47 * <--------AHB-------> | | | |
48 * | | +----+ |
51 * <------SE IRQ------+ +----------------------------+ |
53 * +-----------------------------------------+
55 * Figure 1: GENI based QUP Wrapper
57 * The GENI submodules include primary and secondary sequencers which are
59 * master-slave model, primary sequencer drives both TX & RX operations. On
60 * serial interfaces that operate using peer-to-peer model, primary sequencer
67 * GENI SE Wrapper driver is structured into 2 parts:
84 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core
96 static const char * const icc_path_names[] = {"qup-core", "qup-config",
97 "qup-memory"};
176 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
183 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
185 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); in geni_se_get_qup_hw_version()
224 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
225 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
226 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
227 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
228 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
233 * geni_se_init() - Initialize the GENI serial engine
236 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.
238 * This function is used to initialize the GENI serial engine, configure
239 * receive watermark and ready-for-receive watermarks.
246 geni_se_io_init(se->base); in geni_se_init()
247 geni_se_io_set_mode(se->base); in geni_se_init()
249 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
250 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
252 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
254 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
256 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
258 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
270 * The RX path for the UART is asynchronous and so needs more in geni_se_select_fifo_mode()
274 * - The done and TX-related interrupts are managed manually. in geni_se_select_fifo_mode()
275 * - We don't RX from the main sequencer (we use the secondary) so in geni_se_select_fifo_mode()
276 * we don't need the RX-related interrupts enabled in the main in geni_se_select_fifo_mode()
277 * sequencer for UART. in geni_se_select_fifo_mode()
280 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
284 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
286 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
289 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
292 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
295 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
306 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
310 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
312 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
315 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
318 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
321 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
330 writel(0, se->base + SE_IRQ_EN); in geni_se_select_gpi_mode()
332 val = readl(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_gpi_mode()
334 writel(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_gpi_mode()
336 val = readl(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
339 writel(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
341 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_gpi_mode()
343 val = readl(se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
345 writel(val, se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
349 * geni_se_select_mode() - Select the serial engine transfer mode
377 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
381 * Refer to below examples for detailed bit-field description.
385 * +-----------+-------+-------+-------+-------+
387 * +-----------+-------+-------+-------+-------+
392 * +-----------+-------+-------+-------+-------+
396 * +-----------+-------+-------+-------+-------+
398 * +-----------+-------+-------+-------+-------+
403 * +-----------+-------+-------+-------+-------+
407 * +-----------+-------+-------+-------+-------+
409 * +-----------+-------+-------+-------+-------+
414 * +-----------+-------+-------+-------+-------+
425 * geni_se_config_packing() - Packing configuration of the serial engine
429 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
442 int idx_start = msb_to_lsb ? bpw - 1 : 0; in geni_se_config_packing()
444 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; in geni_se_config_packing()
453 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; in geni_se_config_packing()
463 temp_bpw = temp_bpw - BITS_PER_BYTE; in geni_se_config_packing()
466 cfg[iter - 1] |= PACKING_STOP_BIT; in geni_se_config_packing()
471 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
472 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
475 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
476 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
481 * 0 - 4x8, four words in each entry, max word size of 8 bits in geni_se_config_packing()
482 * 1 - 2x16, two words in each entry, max word size of 16 bits in geni_se_config_packing()
483 * 2 - 1x32, one word in each entry, max word size of 32 bits in geni_se_config_packing()
484 * 3 - undefined in geni_se_config_packing()
487 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
493 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_off()
495 clk_disable_unprepare(se->clk); in geni_se_clks_off()
496 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_off()
497 wrapper->ahb_clks); in geni_se_clks_off()
501 * geni_se_resources_off() - Turn off resources associated with the serial
511 if (has_acpi_companion(se->dev)) in geni_se_resources_off()
514 ret = pinctrl_pm_select_sleep_state(se->dev); in geni_se_resources_off()
526 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_on()
528 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
529 wrapper->ahb_clks); in geni_se_clks_on()
533 ret = clk_prepare_enable(se->clk); in geni_se_clks_on()
535 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
536 wrapper->ahb_clks); in geni_se_clks_on()
541 * geni_se_resources_on() - Turn on resources associated with the serial
551 if (has_acpi_companion(se->dev)) in geni_se_resources_on()
558 ret = pinctrl_pm_select_default_state(se->dev); in geni_se_resources_on()
567 * geni_se_clk_tbl_get() - Get the clock table to program DFS
584 if (se->clk_perf_tbl) { in geni_se_clk_tbl_get()
585 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
586 return se->num_clk_levels; in geni_se_clk_tbl_get()
589 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, in geni_se_clk_tbl_get()
590 sizeof(*se->clk_perf_tbl), in geni_se_clk_tbl_get()
592 if (!se->clk_perf_tbl) in geni_se_clk_tbl_get()
593 return -ENOMEM; in geni_se_clk_tbl_get()
596 freq = clk_round_rate(se->clk, freq + 1); in geni_se_clk_tbl_get()
597 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) in geni_se_clk_tbl_get()
599 se->clk_perf_tbl[i] = freq; in geni_se_clk_tbl_get()
601 se->num_clk_levels = i; in geni_se_clk_tbl_get()
602 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
603 return se->num_clk_levels; in geni_se_clk_tbl_get()
608 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
621 * - if @exact is true then @res_freq / <an_integer> == @req_freq
622 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
642 return -EINVAL; in geni_se_clk_freq_match()
647 new_delta = req_freq - tbl[i] / divider; in geni_se_clk_freq_match()
663 return -EINVAL; in geni_se_clk_freq_match()
674 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
687 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_prep()
691 return -EINVAL; in geni_se_tx_dma_prep()
693 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); in geni_se_tx_dma_prep()
694 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_tx_dma_prep()
695 return -EIO; in geni_se_tx_dma_prep()
700 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_dma_prep()
701 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_dma_prep()
702 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_dma_prep()
703 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_dma_prep()
704 writel(len, se->base + SE_DMA_TX_LEN); in geni_se_tx_dma_prep()
710 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
723 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_prep()
727 return -EINVAL; in geni_se_rx_dma_prep()
729 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); in geni_se_rx_dma_prep()
730 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_rx_dma_prep()
731 return -EIO; in geni_se_rx_dma_prep()
736 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_dma_prep()
737 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_dma_prep()
738 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_dma_prep()
740 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_dma_prep()
741 writel(len, se->base + SE_DMA_RX_LEN); in geni_se_rx_dma_prep()
747 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
756 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_unprep()
758 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_tx_dma_unprep()
759 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); in geni_se_tx_dma_unprep()
764 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
773 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_unprep()
775 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_rx_dma_unprep()
776 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); in geni_se_rx_dma_unprep()
783 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; in geni_icc_get()
785 if (has_acpi_companion(se->dev)) in geni_icc_get()
788 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_get()
792 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); in geni_icc_get()
793 if (IS_ERR(se->icc_paths[i].path)) in geni_icc_get()
800 err = PTR_ERR(se->icc_paths[i].path); in geni_icc_get()
801 if (err != -EPROBE_DEFER) in geni_icc_get()
802 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", in geni_icc_get()
813 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_set_bw()
814 ret = icc_set_bw(se->icc_paths[i].path, in geni_icc_set_bw()
815 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); in geni_icc_set_bw()
817 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", in geni_icc_set_bw()
831 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) in geni_icc_set_tag()
832 icc_set_tag(se->icc_paths[i].path, tag); in geni_icc_set_tag()
841 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_enable()
842 ret = icc_enable(se->icc_paths[i].path); in geni_icc_enable()
844 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", in geni_icc_enable()
858 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_disable()
859 ret = icc_disable(se->icc_paths[i].path); in geni_icc_disable()
861 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", in geni_icc_disable()
873 struct device *dev = &pdev->dev; in geni_se_probe()
880 return -ENOMEM; in geni_se_probe()
882 wrapper->dev = dev; in geni_se_probe()
884 wrapper->base = devm_ioremap_resource(dev, res); in geni_se_probe()
885 if (IS_ERR(wrapper->base)) in geni_se_probe()
886 return PTR_ERR(wrapper->base); in geni_se_probe()
888 if (!has_acpi_companion(&pdev->dev)) { in geni_se_probe()
889 wrapper->ahb_clks[0].id = "m-ahb"; in geni_se_probe()
890 wrapper->ahb_clks[1].id = "s-ahb"; in geni_se_probe()
891 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); in geni_se_probe()
899 dev_dbg(dev, "GENI SE Driver probed\n"); in geni_se_probe()
904 { .compatible = "qcom,geni-se-qup", },
918 MODULE_DESCRIPTION("GENI Serial Engine Driver");