Lines Matching full:drv
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
259 writel_relaxed(value, drv->base + offset); in cpr_write()
262 static u32 cpr_read(struct cpr_drv *drv, u32 offset) in cpr_read() argument
264 return readl_relaxed(drv->base + offset); in cpr_read()
268 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value) in cpr_masked_write() argument
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
275 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
278 static void cpr_irq_clr(struct cpr_drv *drv) in cpr_irq_clr() argument
280 cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL); in cpr_irq_clr()
283 static void cpr_irq_clr_nack(struct cpr_drv *drv) in cpr_irq_clr_nack() argument
285 cpr_irq_clr(drv); in cpr_irq_clr_nack()
286 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_irq_clr_nack()
289 static void cpr_irq_clr_ack(struct cpr_drv *drv) in cpr_irq_clr_ack() argument
291 cpr_irq_clr(drv); in cpr_irq_clr_ack()
292 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_irq_clr_ack()
295 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits) in cpr_irq_set() argument
297 cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits); in cpr_irq_set()
300 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value) in cpr_ctl_modify() argument
302 cpr_masked_write(drv, REG_RBCPR_CTL, mask, value); in cpr_ctl_modify()
305 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner) in cpr_ctl_enable() argument
308 const struct cpr_desc *desc = drv->desc; in cpr_ctl_enable()
314 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); in cpr_ctl_enable()
315 cpr_masked_write(drv, REG_RBCPR_CTL, in cpr_ctl_enable()
319 cpr_irq_set(drv, corner->save_irq); in cpr_ctl_enable()
321 if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV) in cpr_ctl_enable()
325 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val); in cpr_ctl_enable()
328 static void cpr_ctl_disable(struct cpr_drv *drv) in cpr_ctl_disable() argument
330 cpr_irq_set(drv, 0); in cpr_ctl_disable()
331 cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN | in cpr_ctl_disable()
333 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, in cpr_ctl_disable()
336 cpr_irq_clr(drv); in cpr_ctl_disable()
337 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_ctl_disable()
338 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_ctl_disable()
339 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0); in cpr_ctl_disable()
342 static bool cpr_ctl_is_enabled(struct cpr_drv *drv) in cpr_ctl_is_enabled() argument
346 reg_val = cpr_read(drv, REG_RBCPR_CTL); in cpr_ctl_is_enabled()
350 static bool cpr_ctl_is_busy(struct cpr_drv *drv) in cpr_ctl_is_busy() argument
354 reg_val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_ctl_is_busy()
358 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner) in cpr_corner_save() argument
360 corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_corner_save()
361 corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0)); in cpr_corner_save()
364 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner) in cpr_corner_restore() argument
368 const struct cpr_desc *desc = drv->desc; in cpr_corner_restore()
372 gcnt = drv->gcnt; in cpr_corner_restore()
378 cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot); in cpr_corner_restore()
382 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_corner_restore()
384 cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt); in cpr_corner_restore()
386 cpr_write(drv, REG_RBCPR_CTL, ctl); in cpr_corner_restore()
388 cpr_irq_set(drv, irq); in cpr_corner_restore()
389 dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt, in cpr_corner_restore()
408 static int cpr_pre_voltage(struct cpr_drv *drv, in cpr_pre_voltage() argument
412 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_pre_voltage()
414 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
415 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
420 static int cpr_post_voltage(struct cpr_drv *drv, in cpr_post_voltage() argument
424 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_post_voltage()
426 if (drv->tcsr && dir == UP) in cpr_post_voltage()
427 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
432 static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner, in cpr_scale_voltage() argument
438 ret = cpr_pre_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
442 ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV); in cpr_scale_voltage()
444 dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n", in cpr_scale_voltage()
449 ret = cpr_post_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
456 static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv) in cpr_get_cur_perf_state() argument
458 return drv->corner ? drv->corner - drv->corners + 1 : 0; in cpr_get_cur_perf_state()
461 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir) in cpr_scale() argument
466 const struct cpr_desc *desc = drv->desc; in cpr_scale()
471 step_uV = regulator_get_linear_step(drv->vdd_apc); in cpr_scale()
475 corner = drv->corner; in cpr_scale()
477 val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_scale()
496 cpr_irq_clr_nack(drv); in cpr_scale()
502 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
505 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP); in cpr_scale()
517 dev_dbg(drv->dev, in cpr_scale()
519 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
533 cpr_irq_clr_nack(drv); in cpr_scale()
539 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
542 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN); in cpr_scale()
554 dev_dbg(drv->dev, in cpr_scale()
556 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
559 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_scale()
561 cpr_irq_clr_nack(drv); in cpr_scale()
564 drv->corner->last_uV = new_uV; in cpr_scale()
578 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
581 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_scale()
584 cpr_irq_clr_ack(drv); in cpr_scale()
591 struct cpr_drv *drv = dev; in cpr_irq_handler() local
592 const struct cpr_desc *desc = drv->desc; in cpr_irq_handler()
596 mutex_lock(&drv->lock); in cpr_irq_handler()
598 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
599 if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS) in cpr_irq_handler()
600 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
602 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val); in cpr_irq_handler()
604 if (!cpr_ctl_is_enabled(drv)) { in cpr_irq_handler()
605 dev_dbg(drv->dev, "CPR is disabled\n"); in cpr_irq_handler()
607 } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) { in cpr_irq_handler()
608 dev_dbg(drv->dev, "CPR measurement is not ready\n"); in cpr_irq_handler()
609 } else if (!cpr_is_allowed(drv)) { in cpr_irq_handler()
610 val = cpr_read(drv, REG_RBCPR_CTL); in cpr_irq_handler()
611 dev_err_ratelimited(drv->dev, in cpr_irq_handler()
621 cpr_scale(drv, UP); in cpr_irq_handler()
623 cpr_scale(drv, DOWN); in cpr_irq_handler()
625 cpr_irq_clr_nack(drv); in cpr_irq_handler()
627 cpr_irq_clr_nack(drv); in cpr_irq_handler()
630 dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n"); in cpr_irq_handler()
632 dev_dbg(drv->dev, in cpr_irq_handler()
637 cpr_corner_save(drv, drv->corner); in cpr_irq_handler()
640 mutex_unlock(&drv->lock); in cpr_irq_handler()
645 static int cpr_enable(struct cpr_drv *drv) in cpr_enable() argument
649 ret = regulator_enable(drv->vdd_apc); in cpr_enable()
653 mutex_lock(&drv->lock); in cpr_enable()
655 if (cpr_is_allowed(drv) && drv->corner) { in cpr_enable()
656 cpr_irq_clr(drv); in cpr_enable()
657 cpr_corner_restore(drv, drv->corner); in cpr_enable()
658 cpr_ctl_enable(drv, drv->corner); in cpr_enable()
661 mutex_unlock(&drv->lock); in cpr_enable()
666 static int cpr_disable(struct cpr_drv *drv) in cpr_disable() argument
668 mutex_lock(&drv->lock); in cpr_disable()
670 if (cpr_is_allowed(drv)) { in cpr_disable()
671 cpr_ctl_disable(drv); in cpr_disable()
672 cpr_irq_clr(drv); in cpr_disable()
675 mutex_unlock(&drv->lock); in cpr_disable()
677 return regulator_disable(drv->vdd_apc); in cpr_disable()
680 static int cpr_config(struct cpr_drv *drv) in cpr_config() argument
685 const struct cpr_desc *desc = drv->desc; in cpr_config()
688 cpr_write(drv, REG_RBIF_IRQ_EN(0), 0); in cpr_config()
689 cpr_write(drv, REG_RBCPR_CTL, 0); in cpr_config()
695 cpr_write(drv, REG_RBIF_LIMIT, val); in cpr_config()
696 cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT); in cpr_config()
703 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_config()
706 gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000; in cpr_config()
709 drv->gcnt = gcnt; in cpr_config()
712 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000; in cpr_config()
713 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val); in cpr_config()
714 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val, in cpr_config()
721 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val); in cpr_config()
728 cpr_write(drv, REG_RBCPR_CTL, val); in cpr_config()
730 for (i = 0; i < drv->num_corners; i++) { in cpr_config()
731 corner = &drv->corners[i]; in cpr_config()
736 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_config()
738 val = cpr_read(drv, REG_RBCPR_VERSION); in cpr_config()
740 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS; in cpr_config()
748 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_set_performance_state() local
753 mutex_lock(&drv->lock); in cpr_set_performance_state()
755 dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n", in cpr_set_performance_state()
756 __func__, state, cpr_get_cur_perf_state(drv)); in cpr_set_performance_state()
762 corner = drv->corners + state - 1; in cpr_set_performance_state()
763 end = &drv->corners[drv->num_corners - 1]; in cpr_set_performance_state()
764 if (corner > end || corner < drv->corners) { in cpr_set_performance_state()
770 if (drv->corner > corner) in cpr_set_performance_state()
772 else if (drv->corner < corner) in cpr_set_performance_state()
777 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
782 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
783 cpr_ctl_disable(drv); in cpr_set_performance_state()
785 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_set_performance_state()
789 if (cpr_is_allowed(drv)) { in cpr_set_performance_state()
790 cpr_irq_clr(drv); in cpr_set_performance_state()
791 if (drv->corner != corner) in cpr_set_performance_state()
792 cpr_corner_restore(drv, corner); in cpr_set_performance_state()
793 cpr_ctl_enable(drv, corner); in cpr_set_performance_state()
796 drv->corner = corner; in cpr_set_performance_state()
799 mutex_unlock(&drv->lock); in cpr_set_performance_state()
805 cpr_populate_ring_osc_idx(struct cpr_drv *drv) in cpr_populate_ring_osc_idx() argument
807 struct fuse_corner *fuse = drv->fuse_corners; in cpr_populate_ring_osc_idx()
808 struct fuse_corner *end = fuse + drv->desc->num_fuse_corners; in cpr_populate_ring_osc_idx()
809 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx()
814 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); in cpr_populate_ring_osc_idx()
827 struct cpr_drv *drv) in cpr_read_fuse_uV() argument
833 ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); in cpr_read_fuse_uV()
848 static int cpr_fuse_corner_init(struct cpr_drv *drv) in cpr_fuse_corner_init() argument
850 const struct cpr_desc *desc = drv->desc; in cpr_fuse_corner_init()
851 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init()
852 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_fuse_corner_init()
863 step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_fuse_corner_init()
868 fuse = drv->fuse_corners; in cpr_fuse_corner_init()
883 step_volt, drv); in cpr_fuse_corner_init()
902 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); in cpr_fuse_corner_init()
921 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) { in cpr_fuse_corner_init()
927 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
931 dev_err(drv->dev, in cpr_fuse_corner_init()
937 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
941 dev_err(drv->dev, in cpr_fuse_corner_init()
947 dev_dbg(drv->dev, in cpr_fuse_corner_init()
957 struct cpr_drv *drv, in cpr_calculate_scaling() argument
971 ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); in cpr_calculate_scaling()
1076 static int cpr_corner_init(struct cpr_drv *drv) in cpr_corner_init() argument
1078 const struct cpr_desc *desc = drv->desc; in cpr_corner_init()
1079 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_corner_init()
1090 int step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_corner_init()
1096 corner = drv->corners; in cpr_corner_init()
1097 end = &corner[drv->num_corners - 1]; in cpr_corner_init()
1099 cdata = devm_kcalloc(drv->dev, drv->num_corners, in cpr_corner_init()
1109 for (level = 1; level <= drv->num_corners; level++) { in cpr_corner_init()
1110 opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level); in cpr_corner_init()
1119 freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev); in cpr_corner_init()
1127 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1128 dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n", in cpr_corner_init()
1178 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1180 prev_fuse = &drv->fuse_corners[fnum - 1]; in cpr_corner_init()
1189 scaling = cpr_calculate_scaling(quot_offset, drv, in cpr_corner_init()
1219 dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i, in cpr_corner_init()
1227 static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv) in cpr_get_fuses() argument
1229 const struct cpr_desc *desc = drv->desc; in cpr_get_fuses()
1233 fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners, in cpr_get_fuses()
1243 fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1248 fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1254 fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1259 fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1268 static void cpr_set_loop_allowed(struct cpr_drv *drv) in cpr_set_loop_allowed() argument
1270 drv->loop_disabled = false; in cpr_set_loop_allowed()
1273 static int cpr_init_parameters(struct cpr_drv *drv) in cpr_init_parameters() argument
1275 const struct cpr_desc *desc = drv->desc; in cpr_init_parameters()
1278 clk = clk_get(drv->dev, "ref"); in cpr_init_parameters()
1282 drv->ref_clk_khz = clk_get_rate(clk) / 1000; in cpr_init_parameters()
1293 dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n", in cpr_init_parameters()
1299 static int cpr_find_initial_corner(struct cpr_drv *drv) in cpr_find_initial_corner() argument
1306 if (!drv->cpu_clk) { in cpr_find_initial_corner()
1307 dev_err(drv->dev, "cannot get rate from NULL clk\n"); in cpr_find_initial_corner()
1311 end = &drv->corners[drv->num_corners - 1]; in cpr_find_initial_corner()
1312 rate = clk_get_rate(drv->cpu_clk); in cpr_find_initial_corner()
1325 for (iter = drv->corners; iter <= end; iter++) { in cpr_find_initial_corner()
1330 drv->corner = iter; in cpr_find_initial_corner()
1334 drv->corner = iter; in cpr_find_initial_corner()
1337 if (!drv->corner) { in cpr_find_initial_corner()
1338 dev_err(drv->dev, "boot up corner not found\n"); in cpr_find_initial_corner()
1342 dev_dbg(drv->dev, "boot up perf state: %u\n", i); in cpr_find_initial_corner()
1436 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_off() local
1438 return cpr_disable(drv); in cpr_power_off()
1443 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_on() local
1445 return cpr_enable(drv); in cpr_power_on()
1451 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_pd_attach_dev() local
1452 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_pd_attach_dev()
1455 mutex_lock(&drv->lock); in cpr_pd_attach_dev()
1457 dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev)); in cpr_pd_attach_dev()
1466 if (drv->attached_cpu_dev) in cpr_pd_attach_dev()
1478 drv->cpu_clk = devm_clk_get(dev, NULL); in cpr_pd_attach_dev()
1479 if (IS_ERR(drv->cpu_clk)) { in cpr_pd_attach_dev()
1480 ret = PTR_ERR(drv->cpu_clk); in cpr_pd_attach_dev()
1482 dev_err(drv->dev, "could not get cpu clk: %d\n", ret); in cpr_pd_attach_dev()
1485 drv->attached_cpu_dev = dev; in cpr_pd_attach_dev()
1487 dev_dbg(drv->dev, "using cpu clk from: %s\n", in cpr_pd_attach_dev()
1488 dev_name(drv->attached_cpu_dev)); in cpr_pd_attach_dev()
1498 ret = dev_pm_opp_get_opp_count(&drv->pd.dev); in cpr_pd_attach_dev()
1500 dev_err(drv->dev, "could not get OPP count\n"); in cpr_pd_attach_dev()
1503 drv->num_corners = ret; in cpr_pd_attach_dev()
1505 if (drv->num_corners < 2) { in cpr_pd_attach_dev()
1506 dev_err(drv->dev, "need at least 2 OPPs to use CPR\n"); in cpr_pd_attach_dev()
1511 drv->corners = devm_kcalloc(drv->dev, drv->num_corners, in cpr_pd_attach_dev()
1512 sizeof(*drv->corners), in cpr_pd_attach_dev()
1514 if (!drv->corners) { in cpr_pd_attach_dev()
1519 ret = cpr_corner_init(drv); in cpr_pd_attach_dev()
1523 cpr_set_loop_allowed(drv); in cpr_pd_attach_dev()
1525 ret = cpr_init_parameters(drv); in cpr_pd_attach_dev()
1530 ret = cpr_config(drv); in cpr_pd_attach_dev()
1534 ret = cpr_find_initial_corner(drv); in cpr_pd_attach_dev()
1539 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1544 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
1548 dev_info(drv->dev, "driver initialized with %u OPPs\n", in cpr_pd_attach_dev()
1549 drv->num_corners); in cpr_pd_attach_dev()
1552 mutex_unlock(&drv->lock); in cpr_pd_attach_dev()
1561 struct cpr_drv *drv = s->private; in cpr_debug_info_show() local
1565 corner = drv->corner; in cpr_debug_info_show()
1572 gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel)); in cpr_debug_info_show()
1575 ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_debug_info_show()
1578 irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_debug_info_show()
1581 reg = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_debug_info_show()
1607 static void cpr_debugfs_init(struct cpr_drv *drv) in cpr_debugfs_init() argument
1609 drv->debugfs = debugfs_create_dir("qcom_cpr", NULL); in cpr_debugfs_init()
1611 debugfs_create_file("debug_info", 0444, drv->debugfs, in cpr_debugfs_init()
1612 drv, &cpr_debug_info_fops); in cpr_debugfs_init()
1619 struct cpr_drv *drv; in cpr_probe() local
1629 drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); in cpr_probe()
1630 if (!drv) in cpr_probe()
1632 drv->dev = dev; in cpr_probe()
1633 drv->desc = data->cpr_desc; in cpr_probe()
1634 drv->acc_desc = data->acc_desc; in cpr_probe()
1636 drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners, in cpr_probe()
1637 sizeof(*drv->fuse_corners), in cpr_probe()
1639 if (!drv->fuse_corners) in cpr_probe()
1646 drv->tcsr = syscon_node_to_regmap(np); in cpr_probe()
1648 if (IS_ERR(drv->tcsr)) in cpr_probe()
1649 return PTR_ERR(drv->tcsr); in cpr_probe()
1652 drv->base = devm_ioremap_resource(dev, res); in cpr_probe()
1653 if (IS_ERR(drv->base)) in cpr_probe()
1654 return PTR_ERR(drv->base); in cpr_probe()
1660 drv->vdd_apc = devm_regulator_get(dev, "vdd-apc"); in cpr_probe()
1661 if (IS_ERR(drv->vdd_apc)) in cpr_probe()
1662 return PTR_ERR(drv->vdd_apc); in cpr_probe()
1675 drv->cpr_fuses = cpr_get_fuses(drv); in cpr_probe()
1676 if (IS_ERR(drv->cpr_fuses)) in cpr_probe()
1677 return PTR_ERR(drv->cpr_fuses); in cpr_probe()
1679 ret = cpr_populate_ring_osc_idx(drv); in cpr_probe()
1683 ret = cpr_fuse_corner_init(drv); in cpr_probe()
1687 mutex_init(&drv->lock); in cpr_probe()
1692 "cpr", drv); in cpr_probe()
1696 drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name, in cpr_probe()
1698 if (!drv->pd.name) in cpr_probe()
1701 drv->pd.power_off = cpr_power_off; in cpr_probe()
1702 drv->pd.power_on = cpr_power_on; in cpr_probe()
1703 drv->pd.set_performance_state = cpr_set_performance_state; in cpr_probe()
1704 drv->pd.opp_to_performance_state = cpr_get_performance_state; in cpr_probe()
1705 drv->pd.attach_dev = cpr_pd_attach_dev; in cpr_probe()
1707 ret = pm_genpd_init(&drv->pd, NULL, true); in cpr_probe()
1711 ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd); in cpr_probe()
1715 platform_set_drvdata(pdev, drv); in cpr_probe()
1716 cpr_debugfs_init(drv); in cpr_probe()
1723 struct cpr_drv *drv = platform_get_drvdata(pdev); in cpr_remove() local
1725 if (cpr_is_allowed(drv)) { in cpr_remove()
1726 cpr_ctl_disable(drv); in cpr_remove()
1727 cpr_irq_set(drv, 0); in cpr_remove()
1731 pm_genpd_remove(&drv->pd); in cpr_remove()
1733 debugfs_remove_recursive(drv->debugfs); in cpr_remove()