16 #define GPC_CNTR		0x000
18 #define GPC_PGC_CTRL_OFFS	0x0
19 #define GPC_PGC_PUPSCR_OFFS	0x4
20 #define GPC_PGC_PDNSCR_OFFS	0x8
21 #define GPC_PGC_SW2ISO_SHIFT	0x8
22 #define GPC_PGC_SW_SHIFT	0x0
24 #define GPC_PGC_PCI_PDN		0x200
25 #define GPC_PGC_PCI_SR		0x20c
27 #define GPC_PGC_GPU_PDN		0x260
28 #define GPC_PGC_GPU_PUPSCR	0x264
29 #define GPC_PGC_GPU_PDNSCR	0x268
30 #define GPC_PGC_GPU_SR		0x26c
32 #define GPC_PGC_DISP_PDN	0x240
33 #define GPC_PGC_DISP_SR		0x24c
36 #define GPU_VPU_PDN_REQ		BIT(0)
40 #define PGC_DOMAIN_FLAG_NO_PD		BIT(0)
67 	iso = val & 0x3f;  in imx6_pm_domain_power_off()
68 	iso2sw = (val >> 8) & 0x3f;  in imx6_pm_domain_power_off()
72 			   0x1, 0x1);  in imx6_pm_domain_power_off()
84 	return 0;  in imx6_pm_domain_power_off()
103 	for (i = 0; i < pd->num_clks; i++)  in imx6_pm_domain_power_on()
108 			   0x1, 0x1);  in imx6_pm_domain_power_on()
124 	for (i = 0; i < pd->num_clks; i++)  in imx6_pm_domain_power_on()
127 	return 0;  in imx6_pm_domain_power_on()
134 	for (i = 0; ; i++) {  in imx_pgc_get_clocks()
147 	return 0;  in imx_pgc_get_clocks()
160 	for (i = domain->num_clks - 1; i >= 0; i--)  in imx_pgc_put_clocks()
205 	return 0;  in imx_pgc_power_domain_probe()
224 	return 0;  in imx_pgc_power_domain_remove()
242 #define GPC_PGC_DOMAIN_ARM	0
267 		.reg_offs = 0x260,
268 		.cntr_pdn_bit = 0,
276 		.reg_offs = 0x240,
285 		.reg_offs = 0x200,
346 	.max_register = 0x2ac,
366 	for (i = 0; i < num_domains; i++) {  in imx_gpc_old_dt_init()
384 	for (i = 0; i < num_domains; i++)  in imx_gpc_old_dt_init()
394 	return 0;  in imx_gpc_old_dt_init()
397 	for (i = 0; i < num_domains; i++)  in imx_gpc_old_dt_init()
419 		return 0;  in imx_gpc_probe()
421 	base = devm_platform_ioremap_resource(pdev, 0);  in imx_gpc_probe()
511 	return 0;  in imx_gpc_probe()
524 		return 0;  in imx_gpc_remove()
543 	return 0;  in imx_gpc_remove()